Add comments with MSR and CPUID flag names
Reorganize the MSR struct
This commit is contained in:
Alexander Babikov
@@ -128,9 +128,9 @@ uint32_t addr64a_2[8];
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static pc_timer_t *cpu_fast_off_timer = NULL;
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static double cpu_fast_off_period = 0.0;
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#define AMD_SYSCALL_EIP (msr.star & 0xFFFFFFFF)
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#define AMD_SYSCALL_SB ((msr.star >> 32) & 0xFFFF)
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#define AMD_SYSRET_SB ((msr.star >> 48) & 0xFFFF)
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#define AMD_SYSCALL_EIP (msr.amd_star & 0xFFFFFFFF)
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#define AMD_SYSCALL_SB ((msr.amd_star >> 32) & 0xFFFF)
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#define AMD_SYSRET_SB ((msr.amd_star >> 48) & 0xFFFF)
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/* These #define's and enum have been borrowed from Bochs. */
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/* SMM feature masks */
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377
src/cpu/cpu.c
377
src/cpu/cpu.c
File diff suppressed because it is too large
Load Diff
120
src/cpu/cpu.h
120
src/cpu/cpu.h
@@ -226,35 +226,41 @@ typedef union {
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} MMX_REG;
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typedef struct {
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/* IDT WinChip and WinChip 2 MSR's */
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uint32_t tr1; /* 0x00000002, 0x0000000e */
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uint32_t tr12; /* 0x00000002, 0x0000000e */
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uint32_t cesr; /* 0x00000011 */
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/* IBM 386SLC/486SLC/486BL MSRs */
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uint64_t ibm_por; /* 0x00001000 - 386SLC and later */
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uint64_t ibm_crcr; /* 0x00001001 - 386SLC and later */
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uint64_t ibm_por2; /* 0x00001002 - 486SLC and later */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
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/* Weird long MSR's used by the Hyper-V BIOS. */
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uint64_t ecx20; /* 0x00000020, really 0x40000020, but we filter out the top 18 bits
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like a real Deschutes does. */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t bios_updt; /* 0x00000079 */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_hwcr; /* 0x00000083 - AMD K5 and K6 MSR's. */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t bbl_cr_dx[4]; /* 0x00000088 - 0x0000008b */
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uint64_t ia32_pmc[8]; /* 0x000000c1 - 0x000000c8 */
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uint64_t mtrr_cap; /* 0x000000fe */
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/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
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/* IDT WinChip C6/2/VIA Cyrix III MSRs */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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/* AMD K5/K6 MSRs */
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uint64_t amd_hwcr; /* 0x00000083 - all K5 and K6 */
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uint64_t amd_efer; /* 0xc0000080 - all K5 and K6 */
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uint64_t amd_star; /* 0xc0000081 - K6-2 and later */
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uint64_t amd_whcr; /* 0xc0000082 - all K5 and K6 */
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uint64_t amd_uwccr; /* 0xc0000085 - K6-2C and later */
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uint64_t amd_epmr; /* 0xc0000086 - K6-III+/2+ only */
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uint64_t amd_psor; /* 0xc0000087 - K6-2C and later */
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uint64_t amd_pfir; /* 0xc0000088 - K6-2C and later */
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uint64_t amd_l2aar; /* 0xc0000089 - K6-III and later */
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/* Pentium/Pentium MMX MSRs */
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uint32_t tr1; /* 0x00000002 - also on WinChip C6/2 */
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uint32_t tr12; /* 0x0000000e - also on WinChip C6/2 */
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uint32_t cesr; /* 0x00000011 - also on WinChip C6/2 */
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/* Pentium Pro/II MSRs */
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uint64_t apic_base; /* 0x0000001b */
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uint64_t bios_updt; /* 0x00000079 */
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uint64_t bbl_cr_dx[4]; /* 0x00000088 - 0x0000008b */
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uint64_t ia32_pmc[8]; /* 0x000000c1 - 0x000000c8 */
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uint64_t mtrr_cap; /* 0x000000fe */
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uint64_t bbl_cr_addr; /* 0x00000116 */
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uint64_t bbl_cr_decc; /* 0x00000118 */
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uint64_t bbl_cr_ctl; /* 0x00000119 */
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@@ -262,68 +268,32 @@ typedef struct {
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uint64_t bbl_cr_busy; /* 0x0000011b */
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uint64_t bbl_cr_ctl3; /* 0x0000011e */
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/* Pentium II Klamath and Pentium II Deschutes MSR's */
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uint16_t sysenter_cs; /* 0x00000174 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_esp; /* 0x00000175 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_eip; /* 0x00000176 - SYSENTER/SYSEXIT MSR's */
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uint16_t sysenter_cs; /* 0x00000174 - Pentium II and later */
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uint32_t sysenter_esp; /* 0x00000175 - Pentium II and later */
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uint32_t sysenter_eip; /* 0x00000176 - Pentium II and later */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
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uint64_t evntsel0; /* 0x00000186 */
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uint64_t evntsel1; /* 0x00000187 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t debug_ctl; /* 0x000001d9 - Debug Registers Control */
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uint64_t mcg_ctl; /* 0x0000017b */
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uint64_t evntsel0; /* 0x00000186 */
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uint64_t evntsel1; /* 0x00000187 */
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uint64_t debug_ctl; /* 0x000001d9 */
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uint64_t rob_cr_bkuptmpdr6; /* 0x000001e0 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f */
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/* MTTR-related MSRs also present on the VIA Cyrix III */
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uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f (ECX & 0) */
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uint64_t mtrr_physmask[8]; /* 0x00000200 - 0x0000020f (ECX & 1) */
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uint64_t mtrr_fix64k_8000; /* 0x00000250 */
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uint64_t mtrr_fix16k_8000; /* 0x00000258 */
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uint64_t mtrr_fix16k_a000; /* 0x00000259 */
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uint64_t mtrr_fix4k[8]; /* 0x00000268 - 0x0000026f */
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uint64_t mtrr_deftype; /* 0x000002ff */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t pat; /* 0x00000277 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_deftype; /* 0x000002ff */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t mca_ctl[5]; /* 0x00000400, 0x00000404, 0x00000408, 0x0000040c, 0x00000410 - Machine Check Architecture */
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uint64_t pat; /* 0x00000277 - Pentium II Deschutes and later */
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uint64_t mca_ctl[5]; /* 0x00000400, 0x00000404, 0x00000408, 0x0000040c, 0x00000410 */
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uint64_t ecx570; /* 0x00000570 */
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/* IBM 386SLC, 486SLC, and 486BL MSR's */
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uint64_t ibm_por; /* 0x00001000 - Processor Operation Register */
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uint64_t ibm_crcr; /* 0x00001001 - Cache Region Control Register */
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/* IBM 486SLC and 486BL MSR's */
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uint64_t ibm_por2; /* 0x00001002 - Processor Operation Register */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_efer; /* 0xc0000080 */
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/* AMD K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t star; /* 0xc0000081 */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_whcr; /* 0xc0000082 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_uwccr; /* 0xc0000085 */
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/* AMD K6-2P and K6-3P MSR's */
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uint64_t amd_epmr; /* 0xc0000086 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
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uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */
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/* K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_l2aar; /* 0xc0000089 */
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/* Other/Unclassified MSRs */
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uint64_t ecx20; /* 0x00000020, really 0x40000020, but we filter out the top 18 bits
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like a real Deschutes does. */
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} msr_t;
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typedef struct {
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