Merge branch 'master' of https://github.com/86Box/86Box
This commit is contained in:
OBattler
@@ -6,7 +6,7 @@
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Intel PCISet chips from 420TX to 440FX.
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* Implementation of the Intel PCISet chips from 420TX to 440BX.
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*
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*
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*
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@@ -43,9 +43,10 @@ enum
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INTEL_430VX,
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INTEL_430TX,
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INTEL_440FX,
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INTEL_440LX,
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INTEL_440EX,
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INTEL_440LX,
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INTEL_440EX,
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INTEL_440BX,
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INTEL_440GX,
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INTEL_440ZX
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};
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@@ -254,7 +255,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case 0x04: /*Command register*/
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switch (dev->type) {
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case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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default:
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regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
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break;
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@@ -268,7 +269,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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switch (dev->type) {
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case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
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case INTEL_440FX: case INTEL_440LX: case INTEL_440EX:
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
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break;
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}
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@@ -286,7 +287,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440FX:
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regs[0x07] &= ~(val & 0xf9);
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break;
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x07] &= ~(val & 0xf0);
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break;
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}
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@@ -310,7 +311,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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break;
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case 0x12:
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switch (dev->type) {
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x12] = (val & 0xc0);
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i4x0_mask_bar(regs);
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break;
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@@ -318,7 +319,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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break;
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case 0x13:
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switch (dev->type) {
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x13] = val;
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i4x0_mask_bar(regs);
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break;
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@@ -326,7 +327,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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break;
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case 0x2c: case 0x2d: case 0x2e: case 0x2f:
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switch (dev->type) {
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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if (!regs_l[addr]) {
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regs[addr] = val;
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regs_l[addr] = 1;
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@@ -385,6 +386,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440BX:
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regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
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break;
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case INTEL_440GX:
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/* TODO: Understand it more specifically */
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regs[0x50] = (regs[0x50] & 0x2b) | (val & 0x28);
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/*regs[0x50] = (regs[0x50] & 0x2b) | (val & 0xd7);*/
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break;
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case INTEL_440ZX:
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regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
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break;
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@@ -405,6 +411,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440BX: case INTEL_440ZX:
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regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
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break;
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case INTEL_440GX:
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regs[0x51] = (regs[0x50] & 0x88) | (val & 0x08);
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/*regs[0x51] = (regs[0x50] & 0x88) | (val & 0x77);*/
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break;
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}
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break;
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case 0x52: /* Cache Control Register */
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@@ -423,7 +433,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440LX:
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regs[0x52] = (val & 0xd0);
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break;
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x52] = val & 0x07;
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break;
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}
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@@ -443,7 +453,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440LX:
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regs[0x53] = val & 0x0a;
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break;
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case INTEL_440EX: case INTEL_440BX:
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case INTEL_440EX: case INTEL_440BX: case INTEL_440GX:
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/* Not applicable to 440ZX as that does not support ECC. */
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regs[0x53] = val;
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break;
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@@ -519,7 +529,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440LX:
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regs[0x57] = val & 0x11;
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break;
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case INTEL_440BX:
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case INTEL_440BX: case INTEL_440GX:
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regs[0x57] = val & 0x3f;
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break;
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case INTEL_440ZX:
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@@ -635,6 +645,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_430HX:
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case INTEL_440FX:
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case INTEL_440LX: case INTEL_440EX:
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case INTEL_440GX:
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case INTEL_440BX: case INTEL_440ZX:
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regs[addr] = val;
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break;
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@@ -650,7 +661,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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switch (dev->type) {
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||||
case INTEL_430NX: case INTEL_430HX:
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case INTEL_440FX: case INTEL_440LX:
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case INTEL_440EX:
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case INTEL_440EX: case INTEL_440GX:
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case INTEL_440BX: case INTEL_440ZX:
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regs[addr] = val;
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break;
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@@ -661,7 +672,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_430NX: case INTEL_430HX:
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case INTEL_440FX: case INTEL_440LX:
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case INTEL_440EX:
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case INTEL_440BX: case INTEL_440ZX:
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||||
case INTEL_440BX: case INTEL_440GX:
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case INTEL_440ZX:
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regs[addr] = val;
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break;
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case INTEL_430VX:
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@@ -688,6 +700,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440BX:
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regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
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break;
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case INTEL_440GX:
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regs[0x68] = (regs[0x68] & 0xc0) | (val & 0x3f);
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break;
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case INTEL_440ZX:
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regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
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break;
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@@ -697,6 +712,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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switch (dev->type) {
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case INTEL_430NX:
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case INTEL_440BX:
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case INTEL_440GX:
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regs[0x69] = val;
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break;
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case INTEL_430VX:
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@@ -713,6 +729,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440LX:
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case INTEL_440EX:
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case INTEL_440BX:
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case INTEL_440GX:
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regs[addr] = val;
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break;
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case INTEL_440ZX:
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@@ -728,6 +745,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_440LX:
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case INTEL_440EX:
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case INTEL_440BX:
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case INTEL_440GX:
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regs[addr] = val;
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break;
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case INTEL_440ZX:
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@@ -806,7 +824,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_430VX:
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regs[0x73] = val & 0x03;
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break;
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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if (!dev->smram_locked) {
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i4x0_smram_handler_phase0(dev);
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regs[0x73] = (regs[0x72] & 0x38) | (val & 0xc7);
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@@ -826,13 +844,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case 0x75: case 0x76:
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case 0x7b:
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switch (dev->type) {
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[addr] = val;
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}
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break;
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case 0x77:
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switch (dev->type) {
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case INTEL_440BX: case INTEL_440ZX:
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case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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regs[0x77] = val & 0x03;
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}
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break;
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@@ -841,7 +859,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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case INTEL_430VX:
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regs[0x78] = val & 0xcf;
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break;
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case INTEL_440BX: case INTEL_440ZX:
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||||
case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
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||||
regs[0x78] = val & 0x0f;
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break;
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}
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@@ -854,14 +872,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
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if (val & 0x40)
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io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
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break;
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
|
||||
regs[0x79] = val;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x7a:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX: case INTEL_440ZX:
|
||||
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
|
||||
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
|
||||
if (val & 0x40)
|
||||
@@ -875,7 +893,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case INTEL_430LX: case INTEL_430NX:
|
||||
regs[0x7c] = val & 0x8f;
|
||||
break;
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0x7c] = val & 0x1f;
|
||||
break;
|
||||
}
|
||||
@@ -911,7 +930,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case INTEL_440LX:
|
||||
regs[0x80] = val & 0x08;
|
||||
break;
|
||||
case INTEL_440EX:
|
||||
case INTEL_440EX: case INTEL_440GX:
|
||||
regs[0x80] = val & 0x18;
|
||||
break;
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
@@ -923,7 +942,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
switch (dev->type) {
|
||||
case INTEL_430HX: case INTEL_440BX:
|
||||
case INTEL_440FX: case INTEL_440LX:
|
||||
case INTEL_440EX:
|
||||
case INTEL_440EX: case INTEL_440GX:
|
||||
/* Not applicable on 82443ZX. */
|
||||
regs[0x91] &= ~(val & 0x11);
|
||||
break;
|
||||
@@ -932,7 +951,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case 0x92:
|
||||
switch (dev->type) {
|
||||
case INTEL_440LX: case INTEL_440EX:
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0x92] &= ~(val & 0x1f);
|
||||
break;
|
||||
}
|
||||
@@ -956,7 +976,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xb0:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xb0] = (val & 0x80);
|
||||
break;
|
||||
}
|
||||
@@ -969,11 +990,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
regs[0xb1] = (val & 0xa0);
|
||||
break;
|
||||
case INTEL_440GX:
|
||||
regs[0xb1] = (val & 0xa2);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xb4:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xb4] = (val & 0x3f);
|
||||
i4x0_mask_bar(regs);
|
||||
break;
|
||||
@@ -981,7 +1006,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xb9:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xb9] = (val & 0xf0);
|
||||
break;
|
||||
}
|
||||
@@ -989,7 +1015,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
|
||||
case 0xba: case 0xbb:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[addr] = val;
|
||||
break;
|
||||
}
|
||||
@@ -997,7 +1024,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
|
||||
case 0xbc:
|
||||
switch (dev->type) {
|
||||
case INTEL_440EX:
|
||||
case INTEL_440EX: case INTEL_440GX:
|
||||
regs[addr] = (val & 0xf8);
|
||||
break;
|
||||
}
|
||||
@@ -1005,7 +1032,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
|
||||
case 0xbd:
|
||||
switch (dev->type) {
|
||||
case INTEL_440EX:
|
||||
case INTEL_440EX: case INTEL_440GX:
|
||||
regs[addr] = (val & 0xf8);
|
||||
break;
|
||||
}
|
||||
@@ -1013,14 +1040,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
|
||||
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[addr] = val;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xca:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
regs[addr] = val;
|
||||
break;
|
||||
case INTEL_440ZX:
|
||||
@@ -1030,7 +1058,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xcb:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
regs[addr] = val;
|
||||
break;
|
||||
case INTEL_440ZX:
|
||||
@@ -1040,7 +1068,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xcc:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
regs[0xcc] = (val & 0x7f);
|
||||
break;
|
||||
case INTEL_440ZX:
|
||||
@@ -1051,7 +1079,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4:
|
||||
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
if (!regs_l[addr])
|
||||
regs[addr] = val;
|
||||
break;
|
||||
@@ -1059,7 +1088,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xe5: case 0xed:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
if (!regs_l[addr])
|
||||
regs[addr] = (val & 0x3f);
|
||||
break;
|
||||
@@ -1067,7 +1097,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xe7:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xe7] = 0x80;
|
||||
for (i = 0; i < 16; i++)
|
||||
regs_l[0xe0 + i] = !!(val & 0x80);
|
||||
@@ -1079,14 +1110,16 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
break;
|
||||
case 0xf0:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xf0] = (val & 0xc0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xf1:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0xf1] = (val & 0x03);
|
||||
break;
|
||||
}
|
||||
@@ -1097,18 +1130,22 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
regs[0x04] = (val & 0x1f);
|
||||
break;
|
||||
case INTEL_440GX:
|
||||
regs[0x04] = val;
|
||||
}
|
||||
break;
|
||||
case 0x05:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0x05] = (val & 0x01);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x0d: case 0x1b:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[addr] = (val & 0xf8);
|
||||
break;
|
||||
}
|
||||
@@ -1117,7 +1154,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case 0x21: case 0x23:
|
||||
case 0x25: case 0x27:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[addr] = val;
|
||||
break;
|
||||
}
|
||||
@@ -1126,21 +1164,24 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
|
||||
case 0x20: case 0x22:
|
||||
case 0x24: case 0x26:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[addr] = (val & 0xf0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x1f:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0x1f] &= ~(val & 0xf0);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x3e:
|
||||
switch (dev->type) {
|
||||
case INTEL_440BX: case INTEL_440ZX:
|
||||
case INTEL_440BX: case INTEL_440GX:
|
||||
case INTEL_440ZX:
|
||||
regs[0x3e] = (val & 0xed);
|
||||
break;
|
||||
}
|
||||
@@ -1430,6 +1471,29 @@ static void
|
||||
regs[0xa5] = 0x02;
|
||||
regs[0xa7] = 0x1f;
|
||||
break;
|
||||
case INTEL_440GX:
|
||||
regs[0x7a] = (info->local >> 8) & 0xff;
|
||||
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
|
||||
|
||||
regs[0x02] = 0xa0; regs[0x03] = 0x71; /* 82443GX */
|
||||
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
|
||||
regs[0x08] = 0x02;
|
||||
regs[0x10] = 0x08;
|
||||
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
|
||||
regs[0x51] |= 0x20;
|
||||
regs[0x57] = 0x28;
|
||||
regs[0x58] = 0x03;
|
||||
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = regs[0x64] = regs[0x65] = regs[0x66] = regs[0x67] = 0x01;
|
||||
regs[0x72] = 0x02;
|
||||
regs[0x73] = 0x38;
|
||||
regs[0x7b] = 0x38;
|
||||
regs[0x90] = 0x80;
|
||||
regs[0xa0] = (regs[0x7a] & 0x02) ? 0x00 : 0x02;
|
||||
regs[0xa2] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
|
||||
regs[0xa4] = 0x03;
|
||||
regs[0xa5] = 0x02;
|
||||
regs[0xa7] = 0x1f;
|
||||
break;
|
||||
}
|
||||
|
||||
regs[0x04] = 0x06; regs[0x07] = 0x02;
|
||||
@@ -1463,11 +1527,15 @@ static void
|
||||
regs[0x24] = 0xf0; regs[0x25] = 0xff;
|
||||
}
|
||||
|
||||
if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
|
||||
if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440GX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
|
||||
regs = (uint8_t *) dev->regs[1];
|
||||
|
||||
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
|
||||
if(dev->type != INTEL_440GX){
|
||||
regs[0x02] = 0x91; regs[0x03] = 0x71; /* 82443BX */
|
||||
} else {
|
||||
regs[0x02] = 0xa1; regs[0x03] = 0x71; /* 82443GX (They seem to share the same deal*/
|
||||
}
|
||||
regs[0x06] = 0x20; regs[0x07] = 0x02;
|
||||
regs[0x08] = 0x02;
|
||||
regs[0x0a] = 0x04; regs[0x0b] = 0x06;
|
||||
@@ -1677,6 +1745,19 @@ const device_t i440bx_device =
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t i440gx_device =
|
||||
{
|
||||
"Intel 82443GX",
|
||||
DEVICE_PCI,
|
||||
0x8000 | INTEL_440GX,
|
||||
i4x0_init,
|
||||
i4x0_close,
|
||||
i4x0_reset,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t i440zx_device =
|
||||
{
|
||||
|
||||
@@ -735,9 +735,13 @@ CPU cpus_PentiumII[] = {
|
||||
};
|
||||
|
||||
CPU cpus_Xeon[] = {
|
||||
/* Slot 2 Xeons. Literal P2D's with more cache */
|
||||
{"Pentium II Xeon 166", CPU_PENTIUM2D, 166666666, 2.5, 0x653, 0x653, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
|
||||
{"Pentium II Xeon 400", CPU_PENTIUM2D, 400000000, 4.0, 0x653, 0x653, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
|
||||
/* Slot 2 Xeons. Literal P2D's with more cache
|
||||
The <400Mhz Xeons are only meant to not cause any struggle
|
||||
to the recompiler. */
|
||||
{"Pentium II Xeon 75", CPU_PENTIUM2D, 75000000, 1.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9},
|
||||
{"Pentium II Xeon 133", CPU_PENTIUM2D, 133333333, 2.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"Pentium II Xeon 166", CPU_PENTIUM2D, 166666666, 2.5, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
|
||||
{"Pentium II Xeon 400", CPU_PENTIUM2D, 400000000, 4.0, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48},
|
||||
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
|
||||
};
|
||||
|
||||
|
||||
@@ -45,8 +45,11 @@ extern const device_t i440fx_device;
|
||||
extern const device_t i440lx_device;
|
||||
extern const device_t i440ex_device;
|
||||
extern const device_t i440bx_device;
|
||||
extern const device_t i440gx_device;
|
||||
extern const device_t i440zx_device;
|
||||
|
||||
extern const device_t ioapic_device;
|
||||
|
||||
/* OPTi */
|
||||
extern const device_t opti495_device;
|
||||
extern const device_t opti5x7_device;
|
||||
|
||||
@@ -336,6 +336,8 @@ extern int machine_at_p65up5_cp6nd_init(const machine_t *);
|
||||
extern int machine_at_p65up5_cpknd_init(const machine_t *);
|
||||
extern int machine_at_kn97_init(const machine_t *);
|
||||
|
||||
extern int machine_at_lx6_init(const machine_t *);
|
||||
|
||||
extern int machine_at_p6i440e2_init(const machine_t *);
|
||||
|
||||
extern int machine_at_p2bls_init(const machine_t *);
|
||||
@@ -354,9 +356,7 @@ extern const device_t *at_tsunamiatx_get_device(void);
|
||||
#endif
|
||||
|
||||
/* m_at_slot2.c */
|
||||
#if defined(DEV_BRANCH) && defined(NO_SIO)
|
||||
extern int machine_at_s2dge_init(const machine_t *);
|
||||
#endif
|
||||
extern int machine_at_6gxu_init(const machine_t *);
|
||||
|
||||
/* m_at_socket370.c */
|
||||
extern int machine_at_s370slm_init(const machine_t *);
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
*
|
||||
*
|
||||
* Author: RichardG, <richardg867@gmail.com>
|
||||
*
|
||||
* Copyright 2020 RichardG.
|
||||
*/
|
||||
#ifndef POSTCARD_H
|
||||
|
||||
130
src/ioapic.c
Normal file
130
src/ioapic.c
Normal file
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
||||
* running old operating systems and software designed for IBM
|
||||
* PC systems and compatibles from 1981 through fairly recent
|
||||
* system designs based on the PCI bus.
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* Skeleton I/O APIC implementation, currently housing the MPS
|
||||
* table patcher for machines that require it.
|
||||
*
|
||||
*
|
||||
*
|
||||
* Author: RichardG, <richardg867@gmail.com>
|
||||
*
|
||||
* Copyright 2020 RichardG.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#define HAVE_STDARG_H
|
||||
#include <86box/86box.h>
|
||||
#include <86box/io.h>
|
||||
#include <86box/device.h>
|
||||
#include <86box/machine.h>
|
||||
#include <86box/mem.h>
|
||||
#include <86box/chipset.h>
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint8_t dummy;
|
||||
} ioapic_t;
|
||||
|
||||
|
||||
#ifdef ENABLE_IOAPIC_LOG
|
||||
int ioapic_do_log = ENABLE_IOAPIC_LOG;
|
||||
|
||||
|
||||
static void
|
||||
ioapic_log(const char *fmt, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
if (ioapic_do_log) {
|
||||
va_start(ap, fmt);
|
||||
pclog_ex(fmt, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
}
|
||||
#else
|
||||
#define ioapic_log(fmt, ...)
|
||||
#endif
|
||||
|
||||
|
||||
static void
|
||||
ioapic_write(uint16_t port, uint8_t val, void *priv)
|
||||
{
|
||||
uint32_t addr, pcmp;
|
||||
|
||||
/* target POST FF, issued by Award before jumping to the bootloader */
|
||||
if (val != 0xff)
|
||||
return;
|
||||
|
||||
ioapic_log("IOAPIC: Caught POST %02X\n", val);
|
||||
|
||||
/* The _MP_ table must be located in the BIOS area, the EBDA, or the last 1k of conventional
|
||||
memory; at a 16-byte boundary in all cases. Award writes both tables to the BIOS area. */
|
||||
for (addr = 0xf0000; addr <= 0xfffff; addr += 16) {
|
||||
/* check signature for the _MP_ table (Floating Point Structure) */
|
||||
if (mem_readl_phys(addr) != 0x5f504d5f) /* ASCII "_MP_" */
|
||||
continue;
|
||||
|
||||
/* read and check pointer to the PCMP table (Configuration Table) */
|
||||
pcmp = mem_readl_phys(addr + 4);
|
||||
if ((pcmp < 0xf0000) || (pcmp > 0xfffff) || (mem_readl_phys(pcmp) != 0x504d4350)) /* ASCII "PCMP" */
|
||||
continue;
|
||||
|
||||
/* patch over the signature on both tables */
|
||||
ioapic_log("IOAPIC: Patching _MP_ [%08x] and PCMP [%08x] tables\n", addr, pcmp);
|
||||
ram[addr] = ram[addr + 1] = ram[addr + 2] = ram[addr + 3] = 0xff;
|
||||
ram[pcmp] = ram[pcmp + 1] = ram[pcmp + 2] = ram[pcmp + 3] = 0xff;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
ioapic_reset(ioapic_t *dev)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
ioapic_close(void *priv)
|
||||
{
|
||||
ioapic_t *dev = (ioapic_t *) priv;
|
||||
|
||||
io_removehandler(0x80, 1,
|
||||
NULL, NULL, NULL, ioapic_write, NULL, NULL, NULL);
|
||||
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
ioapic_init(const device_t *info)
|
||||
{
|
||||
ioapic_t *dev = (ioapic_t *) malloc(sizeof(ioapic_t));
|
||||
memset(dev, 0, sizeof(ioapic_t));
|
||||
|
||||
ioapic_reset(dev);
|
||||
|
||||
io_sethandler(0x80, 1,
|
||||
NULL, NULL, NULL, ioapic_write, NULL, NULL, NULL);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
||||
const device_t ioapic_device = {
|
||||
"I/O Advanced Programmable Interrupt Controller",
|
||||
DEVICE_AT,
|
||||
0,
|
||||
ioapic_init, ioapic_close, NULL,
|
||||
NULL, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
@@ -108,6 +108,37 @@ machine_at_kn97_init(const machine_t *model)
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
machine_at_lx6_init(const machine_t *model)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = bios_load_linear(L"roms/machines/lx6/LX6C_PZ.B00",
|
||||
0x000e0000, 131072, 0);
|
||||
|
||||
if (bios_only || !ret)
|
||||
return ret;
|
||||
|
||||
machine_at_common_init_ex(model, 2);
|
||||
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
||||
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
|
||||
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
device_add(&i440lx_device);
|
||||
device_add(&piix4e_device);
|
||||
device_add(&keyboard_ps2_pci_device);
|
||||
device_add(&w83977tf_device);
|
||||
device_add(&sst_flash_29ee010_device);
|
||||
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
machine_at_p6i440e2_init(const machine_t *model)
|
||||
{
|
||||
|
||||
@@ -31,6 +31,7 @@
|
||||
#include <86box/hdc_ide.h>
|
||||
#include <86box/keyboard.h>
|
||||
#include <86box/intel_flash.h>
|
||||
#include <86box/sst_flash.h>
|
||||
#include <86box/intel_sio.h>
|
||||
#include <86box/piix.h>
|
||||
#include <86box/sio.h>
|
||||
@@ -41,21 +42,12 @@
|
||||
#include "cpu.h"
|
||||
#include <86box/machine.h>
|
||||
|
||||
#if defined(DEV_BRANCH) && defined(NO_SIO)
|
||||
int
|
||||
machine_at_s2dge_init(const machine_t *model)
|
||||
machine_at_6gxu_init(const machine_t *model)
|
||||
{
|
||||
|
||||
/*
|
||||
440GX AMI Slot 2 motherboard
|
||||
|
||||
This board under a i686 CPU freezes on POST code D0.
|
||||
According to the manual it has to do with the NMI which
|
||||
seems to be related on the I/O APIC. Works fine under a VIA C3.
|
||||
*/
|
||||
int ret;
|
||||
|
||||
ret = bios_load_linear(L"roms/machines/s2dge/2gu7301.rom",
|
||||
ret = bios_load_linear(L"roms/machines/6gxu/6gxu.f1c",
|
||||
0x000c0000, 262144, 0);
|
||||
|
||||
if (bios_only || !ret)
|
||||
@@ -66,33 +58,32 @@ machine_at_s2dge_init(const machine_t *model)
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
||||
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
|
||||
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); /* On-Board SCSI. Not emulated at the moment */
|
||||
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
|
||||
device_add(&i440bx_device); /* i440GX */
|
||||
device_add(&i440gx_device);
|
||||
device_add(&piix4e_device);
|
||||
device_add(&keyboard_ps2_ami_pci_device);
|
||||
device_add(&w83977tf_device);
|
||||
device_add(&intel_flash_bxt_device);
|
||||
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
|
||||
device_add(&keyboard_ps2_pci_device);
|
||||
device_add(&w83977ef_device);
|
||||
device_add(&sst_flash_39sf020_device);
|
||||
spd_register(SPD_TYPE_SDRAM, 0xF, 512);
|
||||
|
||||
hwm_values_t machine_hwm = {
|
||||
{ /* fan speeds */
|
||||
3000, /* CPU1 */
|
||||
0, /* CPU2 */
|
||||
3000 /* Thermal Control */
|
||||
3000, /* Chassis */
|
||||
3000, /* CPU */
|
||||
3000 /* Power */
|
||||
}, { /* temperatures */
|
||||
30, /* MB */
|
||||
0, /* unused */
|
||||
30, /* CPU1 */
|
||||
20 /* unused (CPU2?) */
|
||||
27 /* CPU */
|
||||
}, { /* voltages */
|
||||
2050, /* CPU1 (2.05V by default) */
|
||||
0, /* CPU2 */
|
||||
2050, /* VCORE (2.05V by default) */
|
||||
0, /* unused */
|
||||
3300, /* +3.3V */
|
||||
RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */
|
||||
RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */
|
||||
@@ -107,4 +98,3 @@ machine_at_s2dge_init(const machine_t *model)
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
@@ -176,6 +176,7 @@ machine_at_p65up5_common_init(const machine_t *model, const device_t *northbridg
|
||||
device_add(&keyboard_ps2_ami_pci_device);
|
||||
device_add(&w83877f_device);
|
||||
device_add(&intel_flash_bxt_device);
|
||||
device_add(&ioapic_device);
|
||||
}
|
||||
|
||||
int
|
||||
|
||||
@@ -110,7 +110,7 @@ const machine_t machines[] = {
|
||||
{ "[286 ISA] Award 286 clone", "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_award286_init, NULL },
|
||||
{ "[286 ISA] Phoenix 286 clone", "px286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_px286_init, NULL },
|
||||
{ "[286 ISA] Quadtel 286 clone", "quadt286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL },
|
||||
{ "[286 ISA] MR 286 clone", "mr286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_mr286_init, NULL },
|
||||
{ "[286 ISA] MR 286 clone", "mr286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 16384, 128, 127, machine_at_mr286_init, NULL },
|
||||
{ "[286 ISA] Commodore PC 30 III", "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL },
|
||||
{ "[286 ISA] Compaq Portable II", "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL },
|
||||
{ "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device },
|
||||
@@ -146,7 +146,7 @@ const machine_t machines[] = {
|
||||
{ "[386SX ISA] AMI Unknown 386SX", "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
|
||||
#endif
|
||||
{ "[386SX ISA] Amstrad MegaPC", "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 32, 1, 127, machine_at_wd76c10_init, NULL },
|
||||
{ "[386SX ISA] Commodore SL386SX", "cbm_sl386sx25", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1024, 8192, 512, 127, machine_at_commodore_sl386sx_init, at_commodore_sl386sx_get_device },
|
||||
{ "[386SX ISA] Commodore SL386SX", "cbm_sl386sx25", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1024, 8192, 512, 127,machine_at_commodore_sl386sx_init, at_commodore_sl386sx_get_device },
|
||||
{ "[386SX ISA] DTK 386SX clone", "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
|
||||
{ "[386SX ISA] IBM PS/1 model 2121", "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
|
||||
{ "[386SX ISA] IBM PS/1 m.2121+ISA", "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 2, 6, 1, 63, machine_ps1_m2121_init, NULL },
|
||||
@@ -159,9 +159,9 @@ const machine_t machines[] = {
|
||||
|
||||
/* 386DX machines */
|
||||
{ "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device },
|
||||
{ "[386DX ISA] AMI 386DX clone", "acc386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_acc386_init, NULL },
|
||||
{ "[386DX ISA] ASUS 386DX ISA", "asus386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_asus386_init, NULL },
|
||||
{ "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 32, 1, 127, machine_at_ecs386_init, NULL },
|
||||
{ "[386DX ISA] AMI 386DX clone", "acc386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_acc386_init, NULL },
|
||||
{ "[386DX ISA] ASUS 386DX ISA", "asus386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 16384, 128, 127, machine_at_asus386_init, NULL },
|
||||
{ "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 1, 16, 1, 127, machine_at_ecs386_init, NULL },
|
||||
{ "[386DX ISA] Micronics 386 clone", "micronics386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_micronics386_init, NULL },
|
||||
|
||||
/* 386DX machines which utilize the VLB bus */
|
||||
@@ -234,8 +234,8 @@ const machine_t machines[] = {
|
||||
/* Socket 7 machines */
|
||||
/* 430FX */
|
||||
{ "[Socket 7-3V FX] ASUS P/I-P54TP4XE", "p54tp4xe", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p54tp4xe_init, NULL },
|
||||
{ "[Socket 7-3V FX] QDI Chariot", "chariot", MACHINE_CPUS_PENTIUM_S73VCH, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_chariot_init, NULL },
|
||||
{ "[Socket 7-3V FX] MR 430FX clone", "mr586", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 8, 128, 8, 127, machine_at_mr586_init, NULL },
|
||||
{ "[Socket 7-3V FX] QDI Chariot", "chariot", MACHINE_CPUS_PENTIUM_S73VCH, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 8, 128, 8, 127, machine_at_chariot_init, NULL },
|
||||
{ "[Socket 7-3V FX] MR 430FX clone", "mr586", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_PS2, 8, 128, 8, 127, machine_at_mr586_init, NULL },
|
||||
{ "[Socket 7-3V FX] Intel Advanced/ATX", "thor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_thor_init, NULL },
|
||||
{ "[Socket 7-3V FX] Intel Advanced/EV", "endeavor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 8, 128, 8, 127, machine_at_endeavor_init, at_endeavor_get_device },
|
||||
{ "[Socket 7-3V FX] MR Intel Advanced/ATX", "mrthor", MACHINE_CPUS_PENTIUM_S73V, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_mrthor_init, NULL },
|
||||
@@ -258,7 +258,7 @@ const machine_t machines[] = {
|
||||
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
|
||||
{ "[Socket 7 VX] Epox P55-VA", "p55va", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_p55va_init, NULL },
|
||||
{ "[Socket 7 VX] HP Brio 80xx", "brio80xx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_brio80xx_init, NULL },
|
||||
{ "[Socket 7 VX] Biostar 8500TVX-A", "8500tvxa", {{ "Intel", cpus_Pentium}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL },
|
||||
{ "[Socket 7 VX] Biostar 8500TVX-A", "8500tvxa", {{ "Intel", cpus_Pentium}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_8500tvxa_init, NULL },
|
||||
{ "[Socket 7 VX] Packard Bell PB680", "pb680", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_pb680_init, NULL },
|
||||
|
||||
/* 430TX */
|
||||
@@ -282,26 +282,29 @@ const machine_t machines[] = {
|
||||
|
||||
/* Socket 8 machines */
|
||||
/* 440FX */
|
||||
{ "[Socket 8 FX] Gigabyte GA-686NX", "686nx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_686nx_init, NULL },
|
||||
{ "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 127, machine_at_mb600n_init, NULL },
|
||||
{ "[Socket 8 FX] Biostar MB-8500ttc", "8500ttc", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_8500ttc_init, NULL },
|
||||
{ "[Socket 8 FX] Micronics M6MI", "m6mi", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_m6mi_init, NULL },
|
||||
{ "[Socket 8 FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cp6nd_init, NULL },
|
||||
{ "[Socket 8 FX] Gigabyte GA-686NX", "686nx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_686nx_init, NULL },
|
||||
{ "[Socket 8 FX] PC Partner MB600N", "mb600n", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_mb600n_init, NULL },
|
||||
{ "[Socket 8 FX] Biostar MB-8500ttc", "8500ttc", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_8500ttc_init, NULL },
|
||||
{ "[Socket 8 FX] Micronics M6MI", "m6mi", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_m6mi_init, NULL },
|
||||
{ "[Socket 8 FX] ASUS P/I-P65UP5 (C-P6ND)", "p65up5_cp6nd", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_p65up5_cp6nd_init, NULL },
|
||||
|
||||
|
||||
/* Slot 1 machines */
|
||||
/* 440FX */
|
||||
{ "[Slot 1 FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_p65up5_cpknd_init, NULL },
|
||||
{ "[Slot 1 FX] ASUS KN97", "kn97", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 384, 8, 127, machine_at_kn97_init, NULL },
|
||||
{ "[Slot 1 FX] ASUS P/I-P65UP5 (C-PKND)", "p65up5_cpknd", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_p65up5_cpknd_init, NULL },
|
||||
{ "[Slot 1 FX] ASUS KN97", "kn97", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 127, machine_at_kn97_init, NULL },
|
||||
|
||||
/* 440LX */
|
||||
{ "[Slot 1 LX] Abit LX6", "lx6", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_lx6_init, NULL },
|
||||
|
||||
/* 440EX */
|
||||
{ "[Slot 1 EX] QDI EXCELLENT II", "p6i440e2", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL },
|
||||
{ "[Slot 1 EX] QDI EXCELLENT II", "p6i440e2", {{"Intel", cpus_PentiumII66}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_p6i440e2_init, NULL },
|
||||
|
||||
/* 440BX */
|
||||
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
|
||||
{ "[Slot 1 BX] ASUS P3B-F", "p3bf", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p3bf_init, NULL },
|
||||
{ "[Slot 1 BX] ABit BF6", "bf6", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_bf6_init, NULL },
|
||||
{ "[Slot 1 BX] A-Trend ATC6310BXII", "atc6310bxii", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc6310bxii_init, NULL },
|
||||
{ "[Slot 1 BX] A-Trend ATC6310BXII", "atc6310bxii", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_atc6310bxii_init, NULL },
|
||||
#if defined(DEV_BRANCH) && defined(NO_SIO)
|
||||
{ "[Slot 1 BX] Tyan Tsunami ATX", "tsunamiatx", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_SOUND, 8, 1024, 8, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
|
||||
#endif
|
||||
@@ -309,9 +312,8 @@ const machine_t machines[] = {
|
||||
|
||||
/* Slot 2 machines */
|
||||
/* 440GX */
|
||||
#if defined(DEV_BRANCH) && defined(NO_SIO)
|
||||
{ "[Slot 2 GX] Supermicro S2DGE", "s2dge", {{"Intel", cpus_Xeon}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_s2dge_init, NULL },
|
||||
#endif
|
||||
/* Till the Heap limit issue is resolved. This board will use 1GB max instead of 2GB */
|
||||
{ "[Slot 2 GX] Gigabyte GA-6GXU", "6gxu", {{"Intel", cpus_Xeon}, {"", NULL},{"", NULL},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 16, 1024, 16, 511, machine_at_6gxu_init, NULL },
|
||||
|
||||
/* PGA370 machines */
|
||||
/* 440LX */
|
||||
|
||||
@@ -11,6 +11,7 @@
|
||||
*
|
||||
*
|
||||
* Author: RichardG, <richardg867@gmail.com>
|
||||
*
|
||||
* Copyright 2020 RichardG.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
|
||||
@@ -527,7 +527,7 @@ CPUOBJ := cpu.o cpu_table.o \
|
||||
$(DYNARECOBJ)
|
||||
|
||||
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
|
||||
intel_4x0.o neat.o opti495.o opti5x7.o scamp.o scat.o \
|
||||
intel_4x0.o ioapic.o neat.o opti495.o opti5x7.o scamp.o scat.o \
|
||||
rabbit.o sis_85c471.o sis_85c496.o \
|
||||
via_apollo.o via_vpx.o wd76c10.o
|
||||
|
||||
|
||||
@@ -531,7 +531,7 @@ CPUOBJ := cpu.o cpu_table.o \
|
||||
$(DYNARECOBJ)
|
||||
|
||||
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
|
||||
intel_4x0.o neat.o opti495.o opti5x7.o scamp.o scat.o \
|
||||
intel_4x0.o ioapic.o neat.o opti495.o opti5x7.o scamp.o scat.o \
|
||||
rabbit.o sis_85c471.o sis_85c496.o \
|
||||
via_apollo.o via_vpx.o wd76c10.o
|
||||
|
||||
|
||||
Reference in New Issue
Block a user