Some corrections.
This commit is contained in:
@@ -71,7 +71,7 @@
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#define FLAG_CONFIG_M1_IO_ON 0x00000020
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#define FLAG_NO_IRQ_STEERING 0x00000040
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#define FLAG_NO_BRIDGES 0x00000080
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#define FLAG_TRC_CONTROLS_SRST 0x00000100
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#define FLAG_TRC_CONTROLS_CPURST 0x00000100
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#define FLAG_MECHANISM_MASK FLAG_MECHANISM_1 | FLAG_MECHANISM_2
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#define FLAG_MASK 0x0000007f
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@@ -1089,7 +1089,7 @@ machine_at_r534f_init(const machine_t *model)
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machine_at_common_init_ex(model, 2);
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pci_init(PCI_CONFIG_TYPE_1);
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pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
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pci_register_slot(0x0B, PCI_CARD_NORMAL, 1, 2, 3, 4);
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@@ -1118,7 +1118,7 @@ machine_at_ms5146_init(const machine_t *model)
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machine_at_common_init_ex(model, 2);
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pci_init(PCI_CONFIG_TYPE_1);
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pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
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@@ -1147,7 +1147,7 @@ machine_at_cb52x_si_init(const machine_t *model)
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machine_at_common_init_ex(model, 2);
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pci_init(PCI_CONFIG_TYPE_1);
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pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
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@@ -752,7 +752,7 @@ machine_at_ap5s_init(const machine_t *model)
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machine_at_common_init_ex(model, 2);
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pci_init(PCI_CONFIG_TYPE_1);
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pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
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@@ -781,7 +781,7 @@ machine_at_ms5124_init(const machine_t *model)
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machine_at_common_init_ex(model, 2);
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pci_init(PCI_CONFIG_TYPE_1);
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pci_init(PCI_CONFIG_TYPE_1 | FLAG_TRC_CONTROLS_CPURST);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0xFE, 0xFF, 0, 0);
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pci_register_slot(0x10, PCI_CARD_NORMAL, 1, 2, 3, 4);
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@@ -424,8 +424,8 @@ pci_write(uint16_t port, uint8_t val, UNUSED(void *priv))
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}
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break;
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case 0xcf9:
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if (pci_flags & FLAG_TRC_CONTROLS_SRST)
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cpu_cpusrst_on_sr = !(val & 0x10);
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if (pci_flags & FLAG_TRC_CONTROLS_CPURST)
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cpu_cpurst_on_sr = !(val & 0x10);
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if (!(pci_trc_reg & 4) && (val & 4))
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pci_trc_reset(val);
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