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Fix the Pentium Pro L1 cache amount

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This commit is contained in:
Alexander Babikov
2023-11-05 07:08:33 +05:00
parent 1959665149
commit 33b6166896
1 changed files with 3 additions and 3 deletions
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6
src/cpu/cpu.c
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@@ -2377,9 +2377,9 @@ cpu_CPUID(void)
Instruction TLB: 4 MB pages, fully associative, 2 entries
Data TLB: 4 KB pages, 4-way set associative, 64 entries */
EBX = ECX = 0;
EDX = 0x0C040842; /* Data TLB: 4 MB pages, 4-way set associative, 8 entries
Level 1 instruction cache: 16 KB, 4-way set associative, 32 byte line size
Level 1 data cache: 16 KB, 4-way set associative, 32 byte line size
EDX = 0x06040A42; /* Data TLB: 4 MB pages, 4-way set associative, 8 entries
Level 1 instruction cache: 8 KB, 4-way set associative, 32-byte line size
Level 1 data cache: 8 KB, 2-way set associative, 32 byte line size
Level 2 cache: 256 KB, 4-way set associative, 32 byte line size */
} else
EAX = EBX = ECX = EDX = 0;