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More skew changes, fixed the missing pixels in hdisp in 24bpp mode as well as properly organized hdisp in other bpp modes.

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Clear bit 7 of attr reg 0x10 in the v7 code otherwise it would scramble the colors in 8-bit graphics mode if issued.
This commit is contained in:
TC1995
2021-03-25 21:46:39 +01:00
parent 92a5e09659
commit 37def45e0e
2 changed files with 6 additions and 3 deletions
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6
src/video/vid_et4000w32.c
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@@ -396,10 +396,10 @@ et4000w32p_recalctimings(svga_t *svga)
} else {
/* Also adjust the graphics mode clocks in some cases. */
if ((svga->gdcreg[5] & 0x40) && (svga->bpp != 32)) {
if ((svga->bpp == 15) || (svga->bpp == 16))
svga->hdisp += 16;
if ((svga->bpp == 15) || (svga->bpp == 16) || (svga->bpp == 24))
svga->hdisp += (svga->seqregs[1] & 1) ? 16 : 18;
else
svga->hdisp += 8;
svga->hdisp += (svga->seqregs[1] & 1) ? 8 : 9;
}
}
}

3
src/video/vid_ht216.c
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@@ -628,6 +628,9 @@ ht216_recalctimings(svga_t *svga)
ht216_t *ht216 = (ht216_t *)svga->p;
int high_res_256 = 0;
if (svga->attrregs[0x10] & 0x80)
svga->attrregs[0x10] &= ~0x80; /*Otherwise 8-bit color in graphics mode is a bit busted*/
switch (ht216->clk_sel) {
case 5: svga->clock = (cpuclock * (double)(1ull << 32)) / 65000000.0; break;
case 6: svga->clock = (cpuclock * (double)(1ull << 32)) / 40000000.0; break;