Implemented i686 MSR 404.
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@@ -203,6 +203,7 @@ uint64_t ecx11e_msr = 0;
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uint64_t ecx186_msr = 0;
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uint64_t ecx187_msr = 0;
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uint64_t ecx1e0_msr = 0;
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uint64_t ecx404_msr = 0;
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uint64_t ecx570_msr = 0;
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uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */
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@@ -2877,6 +2878,10 @@ void cpu_RDMSR()
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EAX = mtrr_deftype_msr & 0xffffffff;
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EDX = mtrr_deftype_msr >> 32;
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break;
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case 0x404:
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EAX = ecx404_msr & 0xffffffff;
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EDX = ecx404_msr >> 32;
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break;
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case 0x570:
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EAX = ecx570_msr & 0xffffffff;
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EDX = ecx570_msr >> 32;
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@@ -3293,9 +3298,12 @@ void cpu_WRMSR()
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case 0x2FF:
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mtrr_deftype_msr = EAX | ((uint64_t)EDX << 32);
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break;
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case 0x404:
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ecx404_msr = EAX | ((uint64_t)EDX << 32);
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break;
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case 0x570:
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ecx570_msr = EAX | ((uint64_t)EDX << 32);
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break;
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break;
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default:
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i686_invalid_wrmsr:
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cpu_log("WRMSR: Invalid MSR: %08X\n", ECX);
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