80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

clang-format in src/mem/

Browse Source
This commit is contained in:
Jasmine Iwanek
2022-09-18 17:18:07 -04:00
parent 3fddf4d488
commit 4685da3fca
8 changed files with 2602 additions and 2828 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
src/mem/catalyst_flash.c
View File

@@ -30,14 +30,11 @@
#include <86box/nvr.h>
#include <86box/plat.h>
#define FLAG_WORD 4
#define FLAG_BXB 2
#define FLAG_INV_A16 1
enum
{
enum {
BLOCK_MAIN1,
BLOCK_MAIN2,
BLOCK_DATA1,
@@ -46,8 +43,7 @@ enum
BLOCKS_NUM
};
enum
{
enum {
CMD_SET_READ = 0x00,
CMD_READ_SIGNATURE = 0x90,
CMD_ERASE = 0x20,
@@ -58,9 +54,7 @@ enum
CMD_RESET = 0xFF
};
typedef struct flash_t
{
typedef struct flash_t {
uint8_t command, pad,
pad0, pad1,
*array;
@@ -68,10 +62,8 @@ typedef struct flash_t
mem_mapping_t mapping, mapping_h[2];
} flash_t;
static char flash_path[1024];
static uint8_t
flash_read(uint32_t addr, void *p)
{
@@ -99,7 +91,6 @@ flash_read(uint32_t addr, void *p)
return ret;
}
static uint16_t
flash_readw(uint32_t addr, void *p)
{
@@ -113,7 +104,6 @@ flash_readw(uint32_t addr, void *p)
return *q;
}
static uint32_t
flash_readl(uint32_t addr, void *p)
{
@@ -127,7 +117,6 @@ flash_readl(uint32_t addr, void *p)
return *q;
}
static void
flash_write(uint32_t addr, uint8_t val, void *p)
{
@@ -151,19 +140,16 @@ flash_write(uint32_t addr, uint8_t val, void *p)
}
}
static void
flash_writew(uint32_t addr, uint16_t val, void *p)
{
}
static void
flash_writel(uint32_t addr, uint32_t val, void *p)
{
}
static void
catalyst_flash_add_mappings(flash_t *dev)
{
@@ -184,7 +170,6 @@ catalyst_flash_add_mappings(flash_t *dev)
dev->array, MEM_MAPPING_EXTERNAL | MEM_MAPPING_ROM | MEM_MAPPING_ROMCS, (void *) dev);
}
static void
catalyst_flash_reset(void *priv)
{
@@ -193,7 +178,6 @@ catalyst_flash_reset(void *priv)
dev->command = CMD_RESET;
}
static void *
catalyst_flash_init(const device_t *info)
{
@@ -224,7 +208,6 @@ catalyst_flash_init(const device_t *info)
return dev;
}
static void
catalyst_flash_close(void *p)
{
@@ -241,7 +224,6 @@ catalyst_flash_close(void *p)
free(dev);
}
const device_t catalyst_flash_device = {
.name = "Catalyst 28F010-D Flash BIOS",
.internal_name = "catalyst_flash",

10
src/mem/i2c_eeprom.c
View File

@@ -24,7 +24,6 @@
#include <86box/86box.h>
#include <86box/i2c.h>
typedef struct {
void *i2c;
uint8_t addr, *data, writable;
@@ -33,11 +32,9 @@ typedef struct {
uint8_t addr_len, addr_pos;
} i2c_eeprom_t;
#ifdef ENABLE_I2C_EEPROM_LOG
int i2c_eeprom_do_log = ENABLE_I2C_EEPROM_LOG;
static void
i2c_eeprom_log(const char *fmt, ...)
{
@@ -53,7 +50,6 @@ i2c_eeprom_log(const char *fmt, ...)
# define i2c_eeprom_log(fmt, ...)
#endif
static uint8_t
i2c_eeprom_start(void *bus, uint8_t addr, uint8_t read, void *priv)
{
@@ -69,7 +65,6 @@ i2c_eeprom_start(void *bus, uint8_t addr, uint8_t read, void *priv)
return 1;
}
static uint8_t
i2c_eeprom_read(void *bus, uint8_t addr, void *priv)
{
@@ -83,7 +78,6 @@ i2c_eeprom_read(void *bus, uint8_t addr, void *priv)
return ret;
}
static uint8_t
i2c_eeprom_write(void *bus, uint8_t addr, uint8_t data, void *priv)
{
@@ -109,7 +103,6 @@ i2c_eeprom_write(void *bus, uint8_t addr, uint8_t data, void *priv)
return 1;
}
static void
i2c_eeprom_stop(void *bus, uint8_t addr, void *priv)
{
@@ -120,7 +113,6 @@ i2c_eeprom_stop(void *bus, uint8_t addr, void *priv)
dev->addr_pos = 0;
}
uint8_t
log2i(uint32_t i)
{
@@ -130,7 +122,6 @@ log2i(uint32_t i)
return ret;
}
void *
i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t writable)
{
@@ -158,7 +149,6 @@ i2c_eeprom_init(void *i2c, uint8_t addr, uint8_t *data, uint32_t size, uint8_t w
return dev;
}
void
i2c_eeprom_close(void *dev_handle)
{

29
src/mem/intel_flash.c
View File

@@ -30,14 +30,11 @@
#include <86box/nvr.h>
#include <86box/plat.h>
#define FLAG_WORD 4
#define FLAG_BXB 2
#define FLAG_INV_A16 1
enum
{
enum {
BLOCK_MAIN1,
BLOCK_MAIN2,
BLOCK_MAIN3,
@@ -48,8 +45,7 @@ enum
BLOCKS_NUM
};
enum
{
enum {
CMD_READ_ARRAY = 0xff,
CMD_IID = 0x90,
CMD_READ_STATUS = 0x70,
@@ -61,9 +57,7 @@ enum
CMD_PROGRAM_SETUP_ALT = 0x10
};
typedef struct flash_t
{
typedef struct flash_t {
uint8_t command, status,
pad, flags,
*array;
@@ -77,10 +71,8 @@ typedef struct flash_t
mem_mapping_t mapping[4], mapping_h[16];
} flash_t;
static char flash_path[1024];
static uint8_t
flash_read(uint32_t addr, void *p)
{
@@ -112,7 +104,6 @@ flash_read(uint32_t addr, void *p)
return ret;
}
static uint16_t
flash_readw(uint32_t addr, void *p)
{
@@ -130,7 +121,8 @@ flash_readw(uint32_t addr, void *p)
q = (uint16_t *) &(dev->array[addr]);
ret = *q;
if (dev->flags & FLAG_WORD) switch (dev->command) {
if (dev->flags & FLAG_WORD)
switch (dev->command) {
case CMD_READ_ARRAY:
default:
break;
@@ -150,7 +142,6 @@ flash_readw(uint32_t addr, void *p)
return ret;
}
static uint32_t
flash_readl(uint32_t addr, void *p)
{
@@ -166,7 +157,6 @@ flash_readl(uint32_t addr, void *p)
return *q;
}
static void
flash_write(uint32_t addr, uint8_t val, void *p)
{
@@ -223,7 +213,6 @@ flash_write(uint32_t addr, uint8_t val, void *p)
}
}
static void
flash_writew(uint32_t addr, uint16_t val, void *p)
{
@@ -239,7 +228,8 @@ flash_writew(uint32_t addr, uint16_t val, void *p)
addr ^= 0x10000;
addr &= biosmask;
if (dev->flags & FLAG_WORD) switch (dev->command) {
if (dev->flags & FLAG_WORD)
switch (dev->command) {
case CMD_ERASE_SETUP:
if (val == CMD_ERASE_CONFIRM) {
for (i = 0; i < 6; i++) {
@@ -280,7 +270,6 @@ flash_writew(uint32_t addr, uint16_t val, void *p)
}
}
static void
flash_writel(uint32_t addr, uint32_t val, void *p)
{
@@ -290,7 +279,6 @@ flash_writel(uint32_t addr, uint32_t val, void *p)
#endif
}
static void
intel_flash_add_mappings(flash_t *dev)
{
@@ -337,7 +325,6 @@ intel_flash_add_mappings(flash_t *dev)
}
}
static void
intel_flash_reset(void *priv)
{
@@ -347,7 +334,6 @@ intel_flash_reset(void *priv)
dev->status = 0;
}
static void *
intel_flash_init(const device_t *info)
{
@@ -534,7 +520,6 @@ intel_flash_init(const device_t *info)
return dev;
}
static void
intel_flash_close(void *p)
{

208
src/mem/mem.c
View File

@@ -54,7 +54,6 @@
# define BLOCK_INVALID 0
#endif
mem_mapping_t ram_low_mapping, /* 0..640K mapping */
ram_mid_mapping,
ram_remapped_mapping, /* 640..1024K mapping */
@@ -116,7 +115,6 @@ int purgeable_page_count = 0;
uint8_t high_page = 0; /* if a high (> 4 gb) page was detected */
/* FIXME: re-do this with a 'mem_ops' struct. */
static uint8_t *page_lookupp; /* pagetable mmu_perm lookup */
static uint8_t *readlookupp;
@@ -136,11 +134,9 @@ static size_t ram_size = 0, ram2_size = 0;
static size_t ram_size = 0;
#endif
#ifdef ENABLE_MEM_LOG
int mem_do_log = ENABLE_MEM_LOG;
static void
mem_log(const char *fmt, ...)
{
@@ -156,7 +152,6 @@ mem_log(const char *fmt, ...)
# define mem_log(fmt, ...)
#endif
int
mem_addr_is_ram(uint32_t addr)
{
@@ -165,7 +160,6 @@ mem_addr_is_ram(uint32_t addr)
return (mapping == &ram_low_mapping) || (mapping == &ram_high_mapping) || (mapping == &ram_mid_mapping) || (mapping == &ram_remapped_mapping);
}
void
resetreadlookup(void)
{
@@ -193,7 +187,6 @@ resetreadlookup(void)
high_page = 0;
}
void
flushmmucache(void)
{
@@ -223,7 +216,6 @@ flushmmucache(void)
#endif
}
void
flushmmucache_nopc(void)
{
@@ -245,7 +237,6 @@ flushmmucache_nopc(void)
}
}
void
mem_flush_write_page(uint32_t addr, uint32_t virt)
{
@@ -278,13 +269,11 @@ mem_flush_write_page(uint32_t addr, uint32_t virt)
}
}
#define mmutranslate_read(addr) mmutranslatereal(addr, 0)
#define mmutranslate_write(addr) mmutranslatereal(addr, 1)
#define rammap(x) ((uint32_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 2) & MEM_GRANULARITY_QMASK]
#define rammap64(x) ((uint64_t *) (_mem_exec[(x) >> MEM_GRANULARITY_BITS]))[((x) >> 3) & MEM_GRANULARITY_PMASK]
static __inline uint64_t
mmutranslatereal_normal(uint32_t addr, int rw)
{
@@ -299,8 +288,10 @@ mmutranslatereal_normal(uint32_t addr, int rw)
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
@@ -348,7 +339,6 @@ mmutranslatereal_normal(uint32_t addr, int rw)
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
static __inline uint64_t
mmutranslatereal_pae(uint32_t addr, int rw)
{
@@ -363,8 +353,10 @@ mmutranslatereal_pae(uint32_t addr, int rw)
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
@@ -376,8 +368,10 @@ mmutranslatereal_pae(uint32_t addr, int rw)
if (!(temp & 1)) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
@@ -409,8 +403,10 @@ mmutranslatereal_pae(uint32_t addr, int rw)
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && (((CPL == 3) && !cpl_override) || (cr0 & WP_FLAG)))) {
cr2 = addr;
temp &= 1;
if (CPL == 3) temp |= 4;
if (rw) temp |= 2;
if (CPL == 3)
temp |= 4;
if (rw)
temp |= 2;
cpu_state.abrt = ABRT_PF;
abrt_error = temp;
return 0xffffffffffffffffULL;
@@ -423,7 +419,6 @@ mmutranslatereal_pae(uint32_t addr, int rw)
return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
}
uint64_t
mmutranslatereal(uint32_t addr, int rw)
{
@@ -437,7 +432,6 @@ mmutranslatereal(uint32_t addr, int rw)
return mmutranslatereal_normal(addr, rw);
}
/* This is needed because the old recompiler calls this to check for page fault. */
uint32_t
mmutranslatereal32(uint32_t addr, int rw)
@@ -449,7 +443,6 @@ mmutranslatereal32(uint32_t addr, int rw)
return (uint32_t) mmutranslatereal(addr, rw);
}
static __inline uint64_t
mmutranslate_noabrt_normal(uint32_t addr, int rw)
{
@@ -482,7 +475,6 @@ mmutranslate_noabrt_normal(uint32_t addr, int rw)
return (uint64_t) ((temp & ~0xfff) + (addr & 0xfff));
}
static __inline uint64_t
mmutranslate_noabrt_pae(uint32_t addr, int rw)
{
@@ -514,7 +506,8 @@ mmutranslate_noabrt_pae(uint32_t addr, int rw)
}
addr4 = (temp & ~0xfffULL) + ((addr >> 9) & 0xff8);
temp = rammap64(addr4) & 0x000000ffffffffffULL;;
temp = rammap64(addr4) & 0x000000ffffffffffULL;
;
temp3 = temp & temp4;
if (!(temp & 1) || ((CPL == 3) && !(temp3 & 4) && !cpl_override) || (rw && !(temp3 & 2) && ((CPL == 3) || (cr0 & WP_FLAG))))
@@ -523,7 +516,6 @@ mmutranslate_noabrt_pae(uint32_t addr, int rw)
return ((temp & ~0xfffULL) + ((uint64_t) (addr & 0xfff))) & 0x000000ffffffffffULL;
}
uint64_t
mmutranslate_noabrt(uint32_t addr, int rw)
{
@@ -537,14 +529,12 @@ mmutranslate_noabrt(uint32_t addr, int rw)
return mmutranslate_noabrt_normal(addr, rw);
}
void
mmu_invalidate(uint32_t addr)
{
flushmmucache_cr3();
}
uint8_t
mem_addr_range_match(uint32_t addr, uint32_t start, uint32_t len)
{
@@ -556,7 +546,6 @@ mem_addr_range_match(uint32_t addr, uint32_t start, uint32_t len)
return 1;
}
uint32_t
mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len)
{
@@ -565,7 +554,6 @@ mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len)
return chunk_start + (addr & mask);
}
void
addreadlookup(uint32_t virt, uint32_t phys)
{
@@ -573,9 +561,11 @@ addreadlookup(uint32_t virt, uint32_t phys)
uint32_t a;
#endif
if (virt == 0xffffffff) return;
if (virt == 0xffffffff)
return;
if (readlookup2[virt>>12] != (uintptr_t) LOOKUP_INV) return;
if (readlookup2[virt >> 12] != (uintptr_t) LOOKUP_INV)
return;
if (readlookup[readlnext] != (int) 0xffffffff) {
if ((readlookup[readlnext] == ((es + DI) >> 12)) || (readlookup[readlnext] == ((es + EDI) >> 12)))
@@ -601,7 +591,6 @@ addreadlookup(uint32_t virt, uint32_t phys)
cycles -= 9;
}
void
addwritelookup(uint32_t virt, uint32_t phys)
{
@@ -609,9 +598,11 @@ addwritelookup(uint32_t virt, uint32_t phys)
uint32_t a;
#endif
if (virt == 0xffffffff) return;
if (virt == 0xffffffff)
return;
if (page_lookup[virt >> 12]) return;
if (page_lookup[virt >> 12])
return;
if (writelookup[writelnext] != -1) {
page_lookup[writelookup[writelnext]] = NULL;
@@ -653,7 +644,6 @@ addwritelookup(uint32_t virt, uint32_t phys)
cycles -= 9;
}
uint8_t *
getpccache(uint32_t a)
{
@@ -665,7 +655,8 @@ getpccache(uint32_t a)
if (cr0 >> 31) {
a64 = mmutranslate_read(a64);
if (a64 == 0xffffffffffffffffULL) return ram;
if (a64 == 0xffffffffffffffffULL)
return ram;
}
a64 &= rammask;
@@ -685,7 +676,6 @@ getpccache(uint32_t a)
return (uint8_t *) &ff_pccache;
}
uint8_t
read_mem_b(uint32_t addr)
{
@@ -705,7 +695,6 @@ read_mem_b(uint32_t addr)
return ret;
}
uint16_t
read_mem_w(uint32_t addr)
{
@@ -732,7 +721,6 @@ read_mem_w(uint32_t addr)
return ret;
}
void
write_mem_b(uint32_t addr, uint8_t val)
{
@@ -749,7 +737,6 @@ write_mem_b(uint32_t addr, uint8_t val)
resub_cycles(old_cycles);
}
void
write_mem_w(uint32_t addr, uint16_t val)
{
@@ -777,7 +764,6 @@ write_mem_w(uint32_t addr, uint16_t val)
resub_cycles(old_cycles);
}
uint8_t
readmembl(uint32_t addr)
{
@@ -807,7 +793,6 @@ readmembl(uint32_t addr)
return 0xff;
}
void
writemembl(uint32_t addr, uint8_t val)
{
@@ -840,7 +825,6 @@ writemembl(uint32_t addr, uint8_t val)
map->write_b(addr, val, map->p);
}
/* Read a byte from memory without MMU translation - result of previous MMU translation passed as value. */
uint8_t
readmembl_no_mmut(uint32_t addr, uint32_t a64)
@@ -866,7 +850,6 @@ readmembl_no_mmut(uint32_t addr, uint32_t a64)
return 0xff;
}
/* Write a byte to memory without MMU translation - result of previous MMU translation passed as value. */
void
writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val)
@@ -895,7 +878,6 @@ writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val)
map->write_b(addr, val, map->p);
}
uint16_t
readmemwl(uint32_t addr)
{
@@ -925,8 +907,7 @@ readmemwl(uint32_t addr)
}
}
return readmembl_no_mmut(addr, addr64a[0]) |
(((uint16_t) readmembl_no_mmut(addr + 1, addr64a[1])) << 8);
return readmembl_no_mmut(addr, addr64a[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, addr64a[1])) << 8);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint16_t *) (readlookup2[addr >> 12] + addr);
@@ -950,14 +931,12 @@ readmemwl(uint32_t addr)
return map->read_w(addr, map->p);
if (map && map->read_b) {
return map->read_b(addr, map->p) |
((uint16_t) (map->read_b(addr + 1, map->p)) << 8);
return map->read_b(addr, map->p) | ((uint16_t) (map->read_b(addr + 1, map->p)) << 8);
}
return 0xffff;
}
void
writememwl(uint32_t addr, uint16_t val)
{
@@ -1033,7 +1012,6 @@ writememwl(uint32_t addr, uint16_t val)
}
}
/* Read a word from memory without MMU translation - results of previous MMU translation passed as array. */
uint16_t
readmemwl_no_mmut(uint32_t addr, uint32_t *a64)
@@ -1053,8 +1031,7 @@ readmemwl_no_mmut(uint32_t addr, uint32_t *a64)
return 0xffff;
}
return readmembl_no_mmut(addr, a64[0]) |
(((uint16_t) readmembl_no_mmut(addr + 1, a64[1])) << 8);
return readmembl_no_mmut(addr, a64[0]) | (((uint16_t) readmembl_no_mmut(addr + 1, a64[1])) << 8);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint16_t *) (readlookup2[addr >> 12] + addr);
@@ -1075,14 +1052,12 @@ readmemwl_no_mmut(uint32_t addr, uint32_t *a64)
return map->read_w(addr, map->p);
if (map && map->read_b) {
return map->read_b(addr, map->p) |
((uint16_t) (map->read_b(addr + 1, map->p)) << 8);
return map->read_b(addr, map->p) | ((uint16_t) (map->read_b(addr + 1, map->p)) << 8);
}
return 0xffff;
}
/* Write a word to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val)
@@ -1140,7 +1115,6 @@ writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val)
}
}
uint32_t
readmemll(uint32_t addr)
{
@@ -1184,8 +1158,7 @@ readmemll(uint32_t addr)
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemwl_no_mmut(addr, addr64a) |
(((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16);
return readmemwl_no_mmut(addr, addr64a) | (((uint32_t) readmemwl_no_mmut(addr + 2, &(addr64a[2]))) << 16);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint32_t *) (readlookup2[addr >> 12] + addr);
@@ -1208,19 +1181,14 @@ readmemll(uint32_t addr)
return map->read_l(addr, map->p);
if (map && map->read_w)
return map->read_w(addr, map->p) |
((uint32_t) (map->read_w(addr + 2, map->p)) << 16);
return map->read_w(addr, map->p) | ((uint32_t) (map->read_w(addr + 2, map->p)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->p) |
((uint32_t) (map->read_b(addr + 1, map->p)) << 8) |
((uint32_t) (map->read_b(addr + 2, map->p)) << 16) |
((uint32_t) (map->read_b(addr + 3, map->p)) << 24);
return map->read_b(addr, map->p) | ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->p)) << 24);
return 0xffffffff;
}
void
writememll(uint32_t addr, uint32_t val)
{
@@ -1314,7 +1282,6 @@ writememll(uint32_t addr, uint32_t val)
}
}
/* Read a long from memory without MMU translation - results of previous MMU translation passed as array. */
uint32_t
readmemll_no_mmut(uint32_t addr, uint32_t *a64)
@@ -1334,8 +1301,7 @@ readmemll_no_mmut(uint32_t addr, uint32_t *a64)
return 0xffffffff;
}
return readmemwl_no_mmut(addr, a64) |
((uint32_t) (readmemwl_no_mmut(addr + 2, &(a64[2]))) << 16);
return readmemwl_no_mmut(addr, a64) | ((uint32_t) (readmemwl_no_mmut(addr + 2, &(a64[2]))) << 16);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint32_t *) (readlookup2[addr >> 12] + addr);
@@ -1356,19 +1322,14 @@ readmemll_no_mmut(uint32_t addr, uint32_t *a64)
return map->read_l(addr, map->p);
if (map && map->read_w)
return map->read_w(addr, map->p) |
((uint32_t) (map->read_w(addr + 2, map->p)) << 16);
return map->read_w(addr, map->p) | ((uint32_t) (map->read_w(addr + 2, map->p)) << 16);
if (map && map->read_b)
return map->read_b(addr, map->p) |
((uint32_t) (map->read_b(addr + 1, map->p)) << 8) |
((uint32_t) (map->read_b(addr + 2, map->p)) << 16) |
((uint32_t) (map->read_b(addr + 3, map->p)) << 24);
return map->read_b(addr, map->p) | ((uint32_t) (map->read_b(addr + 1, map->p)) << 8) | ((uint32_t) (map->read_b(addr + 2, map->p)) << 16) | ((uint32_t) (map->read_b(addr + 3, map->p)) << 24);
return 0xffffffff;
}
/* Write a long to memory without MMU translation - results of previous MMU translation passed as array. */
void
writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val)
@@ -1432,7 +1393,6 @@ writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val)
}
}
uint64_t
readmemql(uint32_t addr)
{
@@ -1475,8 +1435,7 @@ readmemql(uint32_t addr)
/* No need to waste precious CPU host cycles on mmutranslate's that were already done, just pass
their result as a parameter to be used if needed. */
return readmemll_no_mmut(addr, addr64a) |
(((uint64_t) readmemll_no_mmut(addr + 4, &(addr64a[4]))) << 32);
return readmemll_no_mmut(addr, addr64a) | (((uint64_t) readmemll_no_mmut(addr + 4, &(addr64a[4]))) << 32);
} else if (readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV) {
mmu_perm = readlookupp[addr >> 12];
return *(uint64_t *) (readlookup2[addr >> 12] + addr);
@@ -1500,7 +1459,6 @@ readmemql(uint32_t addr)
return readmemll(addr) | ((uint64_t) readmemll(addr + 4) << 32);
}
void
writememql(uint32_t addr, uint64_t val)
{
@@ -1599,7 +1557,6 @@ writememql(uint32_t addr, uint64_t val)
}
}
void
do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write)
{
@@ -1649,7 +1606,6 @@ do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write)
}
}
uint8_t
mem_readb_phys(uint32_t addr)
{
@@ -1668,7 +1624,6 @@ mem_readb_phys(uint32_t addr)
return ret;
}
uint16_t
mem_readw_phys(uint32_t addr)
{
@@ -1690,7 +1645,6 @@ mem_readw_phys(uint32_t addr)
return ret;
}
uint32_t
mem_readl_phys(uint32_t addr)
{
@@ -1712,7 +1666,6 @@ mem_readl_phys(uint32_t addr)
return ret;
}
void
mem_read_phys(void *dest, uint32_t addr, int transfer_size)
{
@@ -1732,7 +1685,6 @@ mem_read_phys(void *dest, uint32_t addr, int transfer_size)
}
}
void
mem_writeb_phys(uint32_t addr, uint8_t val)
{
@@ -1748,7 +1700,6 @@ mem_writeb_phys(uint32_t addr, uint8_t val)
}
}
void
mem_writew_phys(uint32_t addr, uint16_t val)
{
@@ -1768,7 +1719,6 @@ mem_writew_phys(uint32_t addr, uint16_t val)
}
}
void
mem_writel_phys(uint32_t addr, uint32_t val)
{
@@ -1788,7 +1738,6 @@ mem_writel_phys(uint32_t addr, uint32_t val)
}
}
void
mem_write_phys(void *src, uint32_t addr, int transfer_size)
{
@@ -1808,7 +1757,6 @@ mem_write_phys(void *src, uint32_t addr, int transfer_size)
}
}
uint8_t
mem_read_ram(uint32_t addr, void *priv)
{
@@ -1823,7 +1771,6 @@ mem_read_ram(uint32_t addr, void *priv)
return ram[addr];
}
uint16_t
mem_read_ramw(uint32_t addr, void *priv)
{
@@ -1838,7 +1785,6 @@ mem_read_ramw(uint32_t addr, void *priv)
return *(uint16_t *) &ram[addr];
}
uint32_t
mem_read_raml(uint32_t addr, void *priv)
{
@@ -1853,7 +1799,6 @@ mem_read_raml(uint32_t addr, void *priv)
return *(uint32_t *) &ram[addr];
}
uint8_t
mem_read_ram_2gb(uint32_t addr, void *priv)
{
@@ -1867,7 +1812,6 @@ mem_read_ram_2gb(uint32_t addr, void *priv)
return ram2[addr - (1 << 30)];
}
uint16_t
mem_read_ram_2gbw(uint32_t addr, void *priv)
{
@@ -1881,7 +1825,6 @@ mem_read_ram_2gbw(uint32_t addr, void *priv)
return *(uint16_t *) &ram2[addr - (1 << 30)];
}
uint32_t
mem_read_ram_2gbl(uint32_t addr, void *priv)
{
@@ -1895,7 +1838,6 @@ mem_read_ram_2gbl(uint32_t addr, void *priv)
return *(uint32_t *) &ram2[addr - (1 << 30)];
}
#ifdef USE_NEW_DYNAREC
static inline int
page_index(page_t *p)
@@ -1903,7 +1845,6 @@ page_index(page_t *p)
return ((uintptr_t) p - (uintptr_t) pages) / sizeof(page_t);
}
void
page_add_to_evict_list(page_t *p)
{
@@ -1914,7 +1855,6 @@ page_add_to_evict_list(page_t *p)
purgeable_page_count++;
}
void
page_remove_from_evict_list(page_t *p)
{
@@ -1930,7 +1870,6 @@ page_remove_from_evict_list(page_t *p)
purgeable_page_count--;
}
void
mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
{
@@ -1956,7 +1895,6 @@ mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
}
}
void
mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
{
@@ -1992,7 +1930,6 @@ mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
}
}
void
mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p)
{
@@ -2042,7 +1979,6 @@ mem_write_ramb_page(uint32_t addr, uint8_t val, page_t *p)
}
}
void
mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
{
@@ -2062,7 +1998,6 @@ mem_write_ramw_page(uint32_t addr, uint16_t val, page_t *p)
}
}
void
mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p)
{
@@ -2083,7 +2018,6 @@ mem_write_raml_page(uint32_t addr, uint32_t val, page_t *p)
}
#endif
void
mem_write_ram(uint32_t addr, uint8_t val, void *priv)
{
@@ -2098,7 +2032,6 @@ mem_write_ram(uint32_t addr, uint8_t val, void *priv)
ram[addr] = val;
}
void
mem_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
@@ -2113,7 +2046,6 @@ mem_write_ramw(uint32_t addr, uint16_t val, void *priv)
*(uint16_t *) &ram[addr] = val;
}
void
mem_write_raml(uint32_t addr, uint32_t val, void *priv)
{
@@ -2128,7 +2060,6 @@ mem_write_raml(uint32_t addr, uint32_t val, void *priv)
*(uint32_t *) &ram[addr] = val;
}
static uint8_t
mem_read_remapped(uint32_t addr, void *priv)
{
@@ -2138,7 +2069,6 @@ mem_read_remapped(uint32_t addr, void *priv)
return ram[addr];
}
static uint16_t
mem_read_remappedw(uint32_t addr, void *priv)
{
@@ -2148,7 +2078,6 @@ mem_read_remappedw(uint32_t addr, void *priv)
return *(uint16_t *) &ram[addr];
}
static uint32_t
mem_read_remappedl(uint32_t addr, void *priv)
{
@@ -2158,7 +2087,6 @@ mem_read_remappedl(uint32_t addr, void *priv)
return *(uint32_t *) &ram[addr];
}
static void
mem_write_remapped(uint32_t addr, uint8_t val, void *priv)
{
@@ -2171,7 +2099,6 @@ mem_write_remapped(uint32_t addr, uint8_t val, void *priv)
ram[addr] = val;
}
static void
mem_write_remappedw(uint32_t addr, uint16_t val, void *priv)
{
@@ -2184,7 +2111,6 @@ mem_write_remappedw(uint32_t addr, uint16_t val, void *priv)
*(uint16_t *) &ram[addr] = val;
}
static void
mem_write_remappedl(uint32_t addr, uint32_t val, void *priv)
{
@@ -2197,7 +2123,6 @@ mem_write_remappedl(uint32_t addr, uint32_t val, void *priv)
*(uint32_t *) &ram[addr] = val;
}
void
mem_invalidate_range(uint32_t start_addr, uint32_t end_addr)
{
@@ -2237,7 +2162,6 @@ mem_invalidate_range(uint32_t start_addr, uint32_t end_addr)
#endif
}
static __inline int
mem_mapping_access_allowed(uint32_t flags, uint16_t access)
{
@@ -2271,7 +2195,6 @@ mem_mapping_access_allowed(uint32_t flags, uint16_t access)
return ret;
}
void
mem_mapping_recalc(uint64_t base, uint64_t size)
{
@@ -2296,34 +2219,27 @@ mem_mapping_recalc(uint64_t base, uint64_t size)
/* Walk mapping list. */
while (map != NULL) {
/* In range? */
if (map->enable && (uint64_t)map->base < ((uint64_t)base + (uint64_t)size) &&
((uint64_t)map->base + (uint64_t)map->size) > (uint64_t)base) {
if (map->enable && (uint64_t) map->base < ((uint64_t) base + (uint64_t) size) && ((uint64_t) map->base + (uint64_t) map->size) > (uint64_t) base) {
uint64_t start = (map->base < base) ? map->base : base;
uint64_t end = (((uint64_t)map->base + (uint64_t)map->size) < (base + size)) ?
((uint64_t)map->base + (uint64_t)map->size) : (base + size);
uint64_t end = (((uint64_t) map->base + (uint64_t) map->size) < (base + size)) ? ((uint64_t) map->base + (uint64_t) map->size) : (base + size);
if (start < map->base)
start = map->base;
for (c = start; c < end; c += MEM_GRANULARITY_SIZE) {
/* CPU */
n = !!in_smm;
if (map->exec &&
mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].x))
if (map->exec && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].x))
_mem_exec[c >> MEM_GRANULARITY_BITS] = map->exec + (c - map->base);
if ((map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
if ((map->write_b || map->write_w || map->write_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
if ((map->read_b || map->read_w || map->read_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping[c >> MEM_GRANULARITY_BITS] = map;
/* Bus */
n |= STATE_BUS;
if ((map->write_b || map->write_w || map->write_l) &&
mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
if ((map->write_b || map->write_w || map->write_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].w))
write_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
if ((map->read_b || map->read_w || map->read_l) &&
mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
if ((map->read_b || map->read_w || map->read_l) && mem_mapping_access_allowed(map->flags, _mem_state[c >> MEM_GRANULARITY_BITS].states[n].r))
read_mapping_bus[c >> MEM_GRANULARITY_BITS] = map;
}
}
@@ -2333,7 +2249,6 @@ mem_mapping_recalc(uint64_t base, uint64_t size)
flushmmucache_cr3();
}
void
mem_mapping_set(mem_mapping_t *map,
uint32_t base,
@@ -2372,7 +2287,6 @@ mem_mapping_set(mem_mapping_t *map,
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_add(mem_mapping_t *map,
uint32_t base,
@@ -2419,14 +2333,12 @@ mem_mapping_add(mem_mapping_t *map,
write_b, write_w, write_l, exec, fl, p);
}
void
mem_mapping_do_recalc(mem_mapping_t *map)
{
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_handler(mem_mapping_t *map,
uint8_t (*read_b)(uint32_t addr, void *p),
@@ -2446,7 +2358,6 @@ mem_mapping_set_handler(mem_mapping_t *map,
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size)
{
@@ -2462,7 +2373,6 @@ mem_mapping_set_addr(mem_mapping_t *map, uint32_t base, uint32_t size)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec)
{
@@ -2471,7 +2381,6 @@ mem_mapping_set_exec(mem_mapping_t *map, uint8_t *exec)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_mask(mem_mapping_t *map, uint32_t mask)
{
@@ -2480,14 +2389,12 @@ mem_mapping_set_mask(mem_mapping_t *map, uint32_t mask)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_set_p(mem_mapping_t *map, void *p)
{
map->p = p;
}
void
mem_mapping_disable(mem_mapping_t *map)
{
@@ -2496,7 +2403,6 @@ mem_mapping_disable(mem_mapping_t *map)
mem_mapping_recalc(map->base, map->size);
}
void
mem_mapping_enable(mem_mapping_t *map)
{
@@ -2505,7 +2411,6 @@ mem_mapping_enable(mem_mapping_t *map)
mem_mapping_recalc(map->base, map->size);
}
void
mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t access)
{
@@ -2540,8 +2445,7 @@ mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t
for (c = 0; c < size; c += MEM_GRANULARITY_SIZE) {
for (i = 0; i < 4; i++) {
if (bitmap & (1 << i)) {
_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] =
(_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate;
_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] = (_mem_state[(c + base) >> MEM_GRANULARITY_BITS].vals[i] & mask) | smstate;
}
}
@@ -2556,7 +2460,6 @@ mem_set_access(uint8_t bitmap, int mode, uint32_t base, uint32_t size, uint16_t
mem_mapping_recalc(base, size);
}
void
mem_a20_init(void)
{
@@ -2573,7 +2476,6 @@ mem_a20_init(void)
}
}
/* Close all the memory mappings. */
void
mem_close(void)
@@ -2589,7 +2491,6 @@ mem_close(void)
base_mapping = last_mapping = 0;
}
static void
mem_add_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
{
@@ -2599,7 +2500,6 @@ mem_add_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
ram + base, MEM_MAPPING_INTERNAL, NULL);
}
static void
mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
{
@@ -2607,7 +2507,6 @@ mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
mem_add_ram_mapping(mapping, base, size);
}
/* Reset the memory state. */
void
mem_reset(void)
@@ -2805,7 +2704,6 @@ mem_reset(void)
#endif
}
void
mem_init(void)
{
@@ -2823,7 +2721,6 @@ mem_init(void)
writelookupp = malloc((1 << 20) * sizeof(uint8_t));
}
void
mem_remap_top(int kb)
{
@@ -2834,7 +2731,8 @@ mem_remap_top(int kb)
static int old_kb = 0;
mem_log("MEM: remapping top %iKB (mem=%i)\n", kb, mem_size);
if (mem_size <= 640) return;
if (mem_size <= 640)
return;
if (kb == 0) {
kb = old_kb;
@@ -2860,8 +2758,7 @@ mem_remap_top(int kb)
#endif
}
mem_set_mem_state_both(start * 1024, size * 1024, set ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) :
(MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
mem_set_mem_state_both(start * 1024, size * 1024, set ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL));
if (set) {
mem_mapping_set_addr(&ram_remapped_mapping, start * 1024, size * 1024);
@@ -2872,13 +2769,13 @@ mem_remap_top(int kb)
flushmmucache();
}
void
mem_reset_page_blocks(void)
{
uint32_t c;
if (pages == NULL) return;
if (pages == NULL)
return;
for (c = 0; c < pages_sz; c++) {
pages[c].write_b = mem_write_ramb_page;
@@ -2896,7 +2793,6 @@ mem_reset_page_blocks(void)
}
}
void
mem_a20_recalc(void)
{

55
src/mem/rom.c
View File

@@ -38,11 +38,9 @@
#include <86box/machine.h>
#include <86box/m_xt_xi8088.h>
#ifdef ENABLE_ROM_LOG
int rom_do_log = ENABLE_ROM_LOG;
static void
rom_log(const char *fmt, ...)
{
@@ -65,8 +63,7 @@ rom_add_path(const char* path)
rom_path_t *rom_path = &rom_paths;
if (rom_paths.path[0] != '\0')
{
if (rom_paths.path[0] != '\0') {
// Iterate to the end of the list.
while (rom_path->next != NULL) {
rom_path = rom_path->next;
@@ -89,7 +86,6 @@ rom_add_path(const char* path)
path_slash(rom_path->path);
}
FILE *
rom_fopen(char *fn, char *mode)
{
@@ -114,7 +110,6 @@ rom_fopen(char *fn, char *mode)
}
}
int
rom_getfile(char *fn, char *s, int size)
{
@@ -144,7 +139,6 @@ rom_getfile(char *fn, char *s, int size)
}
}
int
rom_present(char *fn)
{
@@ -159,7 +153,6 @@ rom_present(char *fn)
return (0);
}
uint8_t
rom_read(uint32_t addr, void *priv)
{
@@ -177,7 +170,6 @@ rom_read(uint32_t addr, void *priv)
return (rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
uint16_t
rom_readw(uint32_t addr, void *priv)
{
@@ -195,7 +187,6 @@ rom_readw(uint32_t addr, void *priv)
return (*(uint16_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
uint32_t
rom_readl(uint32_t addr, void *priv)
{
@@ -213,7 +204,6 @@ rom_readl(uint32_t addr, void *priv)
return (*(uint32_t *) &rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
int
rom_load_linear_oddeven(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
{
@@ -249,7 +239,6 @@ rom_load_linear_oddeven(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
return (1);
}
/* Load a ROM BIOS from its chips, interleaved mode. */
int
rom_load_linear(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
@@ -279,7 +268,6 @@ rom_load_linear(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
return (1);
}
/* Load a ROM BIOS from its chips, linear mode with high bit flipped. */
int
rom_load_linear_inverted(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
@@ -292,12 +280,9 @@ rom_load_linear_inverted(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000)
{
if (addr >= 0x40000) {
addr = 0;
}
else
{
} else {
addr &= 0x03ffff;
}
@@ -321,7 +306,6 @@ rom_load_linear_inverted(char *fn, uint32_t addr, int sz, int off, uint8_t *ptr)
return (1);
}
/* Load a ROM BIOS from its chips, interleaved mode. */
int
rom_load_interleaved(char *fnl, char *fnh, uint32_t addr, int sz, int off, uint8_t *ptr)
@@ -331,21 +315,22 @@ rom_load_interleaved(char *fnl, char *fnh, uint32_t addr, int sz, int off, uint8
int c;
if (fl == NULL || fh == NULL) {
if (fl == NULL) rom_log("ROM: image '%s' not found\n", fnl);
else (void)fclose(fl);
if (fh == NULL) rom_log("ROM: image '%s' not found\n", fnh);
else (void)fclose(fh);
if (fl == NULL)
rom_log("ROM: image '%s' not found\n", fnl);
else
(void) fclose(fl);
if (fh == NULL)
rom_log("ROM: image '%s' not found\n", fnh);
else
(void) fclose(fh);
return (0);
}
/* Make sure we only look at the base-256K offset. */
if (addr >= 0x40000)
{
if (addr >= 0x40000) {
addr = 0;
}
else
{
} else {
addr &= 0x03ffff;
}
@@ -364,7 +349,6 @@ rom_load_interleaved(char *fnl, char *fnh, uint32_t addr, int sz, int off, uint8
return (1);
}
static int
bios_normalize(int n, int up)
{
@@ -378,8 +362,6 @@ bios_normalize(int n, int up)
return temp_n;
}
static uint8_t *
rom_reset(uint32_t addr, int sz)
{
@@ -404,7 +386,6 @@ rom_reset(uint32_t addr, int sz)
return rom;
}
uint8_t
bios_read(uint32_t addr, void *priv)
{
@@ -418,7 +399,6 @@ bios_read(uint32_t addr, void *priv)
return ret;
}
uint16_t
bios_readw(uint32_t addr, void *priv)
{
@@ -432,7 +412,6 @@ bios_readw(uint32_t addr, void *priv)
return ret;
}
uint32_t
bios_readl(uint32_t addr, void *priv)
{
@@ -446,7 +425,6 @@ bios_readl(uint32_t addr, void *priv)
return ret;
}
static void
bios_add(void)
{
@@ -498,7 +476,6 @@ bios_add(void)
}
}
/* These four are for loading the BIOS. */
int
bios_load(char *fn1, char *fn2, uint32_t addr, int sz, int off, int flags)
@@ -547,7 +524,6 @@ bios_load(char *fn1, char *fn2, uint32_t addr, int sz, int off, int flags)
return ret;
}
int
bios_load_linear_combined(char *fn1, char *fn2, int sz, int off)
{
@@ -559,7 +535,6 @@ bios_load_linear_combined(char *fn1, char *fn2, int sz, int off)
return ret;
}
int
bios_load_linear_combined2(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5, int sz, int off)
{
@@ -575,7 +550,6 @@ bios_load_linear_combined2(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5
return ret;
}
int
bios_load_linear_combined2_ex(char *fn1, char *fn2, char *fn3, char *fn4, char *fn5, int sz, int off)
{
@@ -591,7 +565,6 @@ bios_load_linear_combined2_ex(char *fn1, char *fn2, char *fn3, char *fn4, char *
return ret;
}
int
rom_init(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{
@@ -621,7 +594,6 @@ rom_init(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_
return (0);
}
int
rom_init_oddeven(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{
@@ -651,7 +623,6 @@ rom_init_oddeven(rom_t *rom, char *fn, uint32_t addr, int sz, int mask, int off,
return (0);
}
int
rom_init_interleaved(rom_t *rom, char *fnl, char *fnh, uint32_t addr, int sz, int mask, int off, uint32_t flags)
{

22
src/mem/smram.c
View File

@@ -29,17 +29,14 @@
#include <86box/mem.h>
#include <86box/smram.h>
static smram_t *base_smram, *last_smram;
static uint8_t use_separate_smram = 0;
static uint8_t smram[0x40000];
#ifdef ENABLE_SMRAM_LOG
int smram_do_log = ENABLE_SMRAM_LOG;
static void
smram_log(const char *fmt, ...)
{
@@ -55,7 +52,6 @@ smram_log(const char *fmt, ...)
# define smram_log(fmt, ...)
#endif
static uint8_t
smram_read(uint32_t addr, void *priv)
{
@@ -70,7 +66,6 @@ smram_read(uint32_t addr, void *priv)
return dev->mapping.exec[addr - dev->host_base];
}
static uint16_t
smram_readw(uint32_t addr, void *priv)
{
@@ -85,7 +80,6 @@ smram_readw(uint32_t addr, void *priv)
return *(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]);
}
static uint32_t
smram_readl(uint32_t addr, void *priv)
{
@@ -100,7 +94,6 @@ smram_readl(uint32_t addr, void *priv)
return *(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]);
}
static void
smram_write(uint32_t addr, uint8_t val, void *priv)
{
@@ -113,7 +106,6 @@ smram_write(uint32_t addr, uint8_t val, void *priv)
dev->mapping.exec[addr - dev->host_base] = val;
}
static void
smram_writew(uint32_t addr, uint16_t val, void *priv)
{
@@ -126,7 +118,6 @@ smram_writew(uint32_t addr, uint16_t val, void *priv)
*(uint16_t *) &(dev->mapping.exec[addr - dev->host_base]) = val;
}
static void
smram_writel(uint32_t addr, uint32_t val, void *priv)
{
@@ -139,7 +130,6 @@ smram_writel(uint32_t addr, uint32_t val, void *priv)
*(uint32_t *) &(dev->mapping.exec[addr - dev->host_base]) = val;
}
/* Make a backup copy of host_base and size of all the SMRAM structs, needed so that if
the SMRAM mappings change while in SMM, they will be recalculated on return. */
void
@@ -156,7 +146,6 @@ smram_backup_all(void)
}
}
/* Recalculate any mappings, including the backup if returning from SMM. */
void
smram_recalc_all(int ret)
@@ -190,7 +179,6 @@ smram_recalc_all(int ret)
flushmmucache();
}
/* Delete a SMRAM mapping. */
void
smram_del(smram_t *smr)
@@ -233,7 +221,6 @@ smram_del(smram_t *smr)
free(smr);
}
/* Add a SMRAM mapping. */
smram_t *
smram_add(void)
@@ -286,7 +273,6 @@ smram_add(void)
return temp_smram;
}
/* Set memory state in the specified model (normal or SMM) according to the specified flags,
separately for bus and CPU. */
void
@@ -298,7 +284,6 @@ smram_map_ex(int bus, int smm, uint32_t addr, uint32_t size, int is_smram)
mem_set_access_smram_cpu(smm, addr, size, is_smram);
}
/* Set memory state in the specified model (normal or SMM) according to the specified flags. */
void
smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
@@ -307,7 +292,6 @@ smram_map(int smm, uint32_t addr, uint32_t size, int is_smram)
smram_map_ex(1, smm, addr, size, is_smram);
}
/* Disable a specific SMRAM mapping. */
void
smram_disable(smram_t *smr)
@@ -328,7 +312,6 @@ smram_disable(smram_t *smr)
}
}
/* Disable all SMRAM mappings. */
void
smram_disable_all(void)
@@ -343,7 +326,6 @@ smram_disable_all(void)
}
}
/* Enable SMRAM mappings according to flags for both normal and SMM modes, separately for bus
and CPU. */
void
@@ -385,7 +367,6 @@ smram_enable_ex(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t si
smram_disable(smr);
}
/* Enable SMRAM mappings according to flags for both normal and SMM modes. */
void
smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size, int flags_normal, int flags_smm)
@@ -393,7 +374,6 @@ smram_enable(smram_t *smr, uint32_t host_base, uint32_t ram_base, uint32_t size,
smram_enable_ex(smr, host_base, ram_base, size, flags_normal, flags_normal, flags_smm, flags_smm);
}
/* Checks if a SMRAM mapping is enabled or not. */
int
smram_enabled(smram_t *smr)
@@ -408,7 +388,6 @@ smram_enabled(smram_t *smr)
return ret;
}
/* Changes the SMRAM state. */
void
smram_state_change(smram_t *smr, int smm, int flags)
@@ -421,7 +400,6 @@ smram_state_change(smram_t *smr, int smm, int flags)
smram_map(smm, smr->host_base, smr->size, flags);
}
void
smram_set_separate_smram(uint8_t set)
{

15
src/mem/spd.c
View File

@@ -28,20 +28,16 @@
#include <86box/version.h>
#include <86box/machine.h>
#define SPD_ROLLUP(x) ((x) >= 16 ? ((x) -15) : (x))
int spd_present = 0;
spd_t *spd_modules[SPD_MAX_SLOTS];
static const device_t spd_device;
#ifdef ENABLE_SPD_LOG
int spd_do_log = ENABLE_SPD_LOG;
static void
spd_log(const char *fmt, ...)
{
@@ -57,7 +53,6 @@ spd_log(const char *fmt, ...)
# define spd_log(fmt, ...)
#endif
static void
spd_close(void *priv)
{
@@ -71,7 +66,6 @@ spd_close(void *priv)
spd_present = 0;
}
static void *
spd_init(const device_t *info)
{
@@ -87,7 +81,6 @@ spd_init(const device_t *info)
return &spd_modules;
}
int
comp_ui16_rev(const void *elem1, const void *elem2)
{
@@ -96,7 +89,6 @@ comp_ui16_rev(const void *elem1, const void *elem2)
return ((a > b) ? -1 : ((a < b) ? 1 : 0));
}
void
spd_populate(uint16_t *rows, uint8_t slot_count, uint16_t total_size, uint16_t min_module_size, uint16_t max_module_size, uint8_t enable_asym)
{
@@ -166,7 +158,6 @@ spd_populate(uint16_t *rows, uint8_t slot_count, uint16_t total_size, uint16_t m
}
}
static int
spd_write_part_no(char *part_no, char *type, uint16_t size)
{
@@ -182,7 +173,6 @@ spd_write_part_no(char *part_no, char *type, uint16_t size)
return sprintf(part_no, EMU_NAME "-%s-%03d%c", type, size, size_unit);
}
void
spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
{
@@ -343,7 +333,6 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
device_add(&spd_device);
}
void
spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
@@ -399,7 +388,6 @@ spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit
}
}
/* Needed for 430LX. */
void
spd_write_drbs_with_ext(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
@@ -449,7 +437,6 @@ spd_write_drbs_with_ext(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t
}
}
/* Used by ALi M1531 and M1541/2. */
void
spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
@@ -501,7 +488,6 @@ spd_write_drbs_interleaved(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint
}
}
/* This is needed because the ALi M1621 does this stuff completely differently,
as it has DRAM bank registers instead of DRAM row boundary registers. */
void
@@ -576,7 +562,6 @@ spd_write_drbs_ali1621(uint8_t *regs, uint8_t reg_min, uint8_t reg_max)
}
}
static const device_t spd_device = {
.name = "Serial Presence Detect ROMs",
.internal_name = "spd",

25
src/mem/sst_flash.c
View File

@@ -32,9 +32,7 @@
#include <86box/plat.h>
#include <86box/m_xt_xi8088.h>
typedef struct sst_t
{
typedef struct sst_t {
uint8_t manufacturer, id, has_bbp, is_39,
page_bytes, sdp, bbp_first_8k, bbp_last_8k;
@@ -54,10 +52,8 @@ typedef struct sst_t
pc_timer_t page_write_timer;
} sst_t;
static char flash_path[1024];
#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */
#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */
#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */
@@ -88,7 +84,6 @@ static char flash_path[1024];
#define SIZE_2M 0x040000
#define SIZE_4M 0x080000
static void
sst_sector_erase(sst_t *dev, uint32_t addr)
{
@@ -103,13 +98,13 @@ sst_sector_erase(sst_t *dev, uint32_t addr)
dev->dirty = 1;
}
static void
sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
{
uint32_t base = 0x00000, size = dev->size;
if (dev->command_state == 5) switch (val) {
if (dev->command_state == 5)
switch (val) {
case SST_CHIP_ERASE:
if (dev->bbp_first_8k & 0x01) {
base += 0x2000;
@@ -143,7 +138,9 @@ sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
default:
dev->command_state = 0;
break;
} else switch (val) {
}
else
switch (val) {
case SST_ERASE:
dev->command_state = 3;
break;
@@ -180,7 +177,6 @@ sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
}
}
static void
sst_page_write(void *priv)
{
@@ -206,7 +202,6 @@ sst_page_write(void *priv)
timer_disable(&dev->page_write_timer);
}
static uint8_t
sst_read_id(uint32_t addr, void *p)
{
@@ -233,7 +228,6 @@ sst_read_id(uint32_t addr, void *p)
return ret;
}
static void
sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val)
{
@@ -247,7 +241,6 @@ sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val)
timer_on_auto(&dev->page_write_timer, 210.0);
}
static void
sst_write(uint32_t addr, uint8_t val, void *p)
{
@@ -320,7 +313,6 @@ sst_write(uint32_t addr, uint8_t val, void *p)
}
}
static uint8_t
sst_read(uint32_t addr, void *p)
{
@@ -339,7 +331,6 @@ sst_read(uint32_t addr, void *p)
return ret;
}
static uint16_t
sst_readw(uint32_t addr, void *p)
{
@@ -358,7 +349,6 @@ sst_readw(uint32_t addr, void *p)
return ret;
}
static uint32_t
sst_readl(uint32_t addr, void *p)
{
@@ -377,7 +367,6 @@ sst_readl(uint32_t addr, void *p)
return ret;
}
static void
sst_add_mappings(sst_t *dev)
{
@@ -414,7 +403,6 @@ sst_add_mappings(sst_t *dev)
}
}
static void *
sst_init(const device_t *info)
{
@@ -460,7 +448,6 @@ sst_init(const device_t *info)
return dev;
}
static void
sst_close(void *p)
{