NEC TEST1 instruction (#4)

This commit is contained in:
Cacodemon345
2022-09-05 01:11:04 +06:00
committed by GitHub
parent 71dde8658b
commit 474ab60c97

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@@ -1716,7 +1716,7 @@ execx86(int cycs)
case 0x28: /* ROL4 r/m */ case 0x28: /* ROL4 r/m */
{ {
do_mod_rm(); do_mod_rm();
wait(22, 0); wait(21, 0);
{ {
uint8_t temp_val = geteab(); uint8_t temp_val = geteab();
uint8_t temp_al = AL; uint8_t temp_al = AL;
@@ -1735,7 +1735,7 @@ execx86(int cycs)
case 0x2a: /* ROR4 r/m */ case 0x2a: /* ROR4 r/m */
{ {
do_mod_rm(); do_mod_rm();
wait(22, 0); wait(21, 0);
{ {
uint8_t temp_val = geteab(); uint8_t temp_val = geteab();
uint8_t temp_al = AL; uint8_t temp_al = AL;
@@ -1748,6 +1748,22 @@ execx86(int cycs)
handled = 1; handled = 1;
break; break;
} }
case 0x10: /* TEST1 r8/m8, CL*/
case 0x11: /* TEST1 r16/m16, CL*/
case 0x18: /* TEST1 r8/m8, imm3 */
case 0x19: /* TEST1 r16/m16, imm4 */
{
bits = 8 << (opcode & 0x1);
do_mod_rm();
wait(3, 0);
{
uint8_t bit = (opcode & 0x8) ? (pfq_fetchb() & 0x7) : (CL & 0xF);
read_ea(0, bits);
set_zf_ex(!(cpu_data & (1 << bit)));
cpu_state.flags &= ~(V_FLAG | C_FLAG);
}
}
default: { default: {
opcode = orig_opcode; opcode = orig_opcode;
break; break;