80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

Add files via upload

Browse Source
This commit is contained in:
nerd73
2019-12-16 18:10:19 -07:00
committed by GitHub
parent 2ce2ea23d0
commit 4e8bcfd6ad
5 changed files with 145 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/808x.c
View File

@@ -915,7 +915,10 @@ reset_common(int hard)
cr0 = 1 << 30;
else
cr0 = 0;
cpu_cache_int_enabled = 0;
if (isibmcpu)
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
cpu_update_waitstates();
cr4 = 0;
cpu_state.eflags = 0;

82
src/cpu/cpu.c
View File

@@ -145,6 +145,7 @@ int is286,
is386,
is486,
cpu_iscyrix,
isibmcpu,
israpidcad,
is_pentium;
@@ -255,8 +256,9 @@ cpu_set(void)
is8086 = (cpu_s->cpu_type > CPU_8088);
is286 = (cpu_s->cpu_type >= CPU_286);
is386 = (cpu_s->cpu_type >= CPU_386SX);
isibmcpu = (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL);
israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD);
is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD);
is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL );
is_pentium = (cpu_s->cpu_type >= CPU_WINCHIP);
hasfpu = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD);
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
@@ -265,7 +267,8 @@ cpu_set(void)
cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86);
#endif
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC);
cpu_16bitbus = (cpu_s->cpu_type == CPU_286 || cpu_s->cpu_type == CPU_386SX || cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC );
if (cpu_s->multi) {
if (cpu_s->pci_speed)
cpu_busspeed = cpu_s->pci_speed;
@@ -484,6 +487,7 @@ cpu_set(void)
timing_jmp_pm_gate = 38;
break;
case CPU_IBM386SLC:
case CPU_386SX:
timing_rr = 2; /*register dest - register src*/
timing_rm = 6; /*register dest - memory src*/
@@ -546,6 +550,80 @@ cpu_set(void)
timing_jmp_pm_gate = 45;
break;
case CPU_IBM486SLC:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else
x86_setopcodes(ops_386, ops_486_0f);
#endif
timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/
timing_mr = 5; /*memory dest - register src*/
timing_mm = 3;
timing_rml = 4; /*register dest - memory src long*/
timing_mrl = 5; /*memory dest - register src long*/
timing_mml = 5;
timing_bt = 3-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
timing_int = 4;
timing_int_rm = 26;
timing_int_v86 = 82;
timing_int_pm = 44;
timing_int_pm_outer = 71;
timing_iret_rm = 15;
timing_iret_v86 = 36; /*unknown*/
timing_iret_pm = 20;
timing_iret_pm_outer = 36;
timing_call_rm = 18;
timing_call_pm = 20;
timing_call_pm_gate = 35;
timing_call_pm_gate_inner = 69;
timing_retf_rm = 13;
timing_retf_pm = 17;
timing_retf_pm_outer = 35;
timing_jmp_rm = 17;
timing_jmp_pm = 19;
timing_jmp_pm_gate = 32;
timing_misaligned = 3;
break;
case CPU_IBM486BL:
#ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
#else
x86_setopcodes(ops_386, ops_486_0f);
#endif
timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/
timing_mr = 3; /*memory dest - register src*/
timing_mm = 3;
timing_rml = 2; /*register dest - memory src long*/
timing_mrl = 3; /*memory dest - register src long*/
timing_mml = 3;
timing_bt = 3-1; /*branch taken*/
timing_bnt = 1; /*branch not taken*/
timing_int = 4;
timing_int_rm = 26;
timing_int_v86 = 82;
timing_int_pm = 44;
timing_int_pm_outer = 71;
timing_iret_rm = 15;
timing_iret_v86 = 36; /*unknown*/
timing_iret_pm = 20;
timing_iret_pm_outer = 36;
timing_call_rm = 18;
timing_call_pm = 20;
timing_call_pm_gate = 35;
timing_call_pm_gate_inner = 69;
timing_retf_rm = 13;
timing_retf_pm = 17;
timing_retf_pm_outer = 35;
timing_jmp_rm = 17;
timing_jmp_pm = 19;
timing_jmp_pm_gate = 32;
timing_misaligned = 3;
break;
case CPU_RAPIDCAD:
timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/

57
src/cpu/cpu.h
View File

@@ -31,39 +31,42 @@
#define CPU_286 2 /* 286 class CPUs */
#define CPU_386SX 3 /* 386 class CPUs */
#define CPU_386DX 4
#define CPU_RAPIDCAD 5
#define CPU_486SLC 6
#define CPU_486DLC 7
#define CPU_i486SX 8 /* 486 class CPUs */
#define CPU_Am486SX 9
#define CPU_Cx486S 10
#define CPU_i486DX 11
#define CPU_Am486DX 12
#define CPU_Cx486DX 13
#define CPU_iDX4 14
#define CPU_Cx5x86 15
#define CPU_WINCHIP 16 /* 586 class CPUs */
#define CPU_PENTIUM 17
#define CPU_PENTIUMMMX 18
#define CPU_Cx6x86 19
#define CPU_Cx6x86MX 20
#define CPU_Cx6x86L 21
#define CPU_CxGX1 22
#define CPU_IBM386SLC 5
#define CPU_IBM486SLC 6
#define CPU_IBM486BL 7
#define CPU_RAPIDCAD 8
#define CPU_486SLC 9
#define CPU_486DLC 10
#define CPU_i486SX 11 /* 486 class CPUs */
#define CPU_Am486SX 12
#define CPU_Cx486S 13
#define CPU_i486DX 14
#define CPU_Am486DX 15
#define CPU_Cx486DX 16
#define CPU_iDX4 17
#define CPU_Cx5x86 18
#define CPU_WINCHIP 19 /* 586 class CPUs */
#define CPU_PENTIUM 20
#define CPU_PENTIUMMMX 21
#define CPU_Cx6x86 22
#define CPU_Cx6x86MX 23
#define CPU_Cx6x86L 24
#define CPU_CxGX1 25
#ifdef DEV_BRANCH
#ifdef USE_AMD_K
#define CPU_K5 23
#define CPU_5K86 24
#define CPU_K6 25
#define CPU_K5 26
#define CPU_5K86 27
#define CPU_K6 28
#endif
#endif
#ifdef DEV_BRANCH
#ifdef USE_I686
#define CPU_PENTIUMPRO 26 /* 686 class CPUs */
#define CPU_PENTIUMPRO 29 /* 686 class CPUs */
#if 0
# define CPU_PENTIUM2 27
# define CPU_PENTIUM2D 28
# define CPU_PENTIUM2 30
# define CPU_PENTIUM2D 31
#else
# define CPU_PENTIUM2D 27
# define CPU_PENTIUM2D 30
#endif
#endif
#endif
@@ -102,6 +105,9 @@ extern CPU cpus_Am386SX[];
extern CPU cpus_Am386DX[];
extern CPU cpus_486SLC[];
extern CPU cpus_486DLC[];
extern CPU cpus_IBM386SLC[];
extern CPU cpus_IBM486SLC[];
extern CPU cpus_IBM486BL[];
extern CPU cpus_i486[];
extern CPU cpus_Am486[];
extern CPU cpus_Cx486[];
@@ -329,6 +335,7 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is286, is386, is486;
extern int isibmcpu;
extern int is_rapidcad;
extern int hasfpu;
#define CPU_FEATURE_RDTSC (1 << 0)

26
src/cpu/cpu_table.c
View File

@@ -173,7 +173,33 @@ CPU cpus_Am386DX[] = {
{"Am386DX/40", CPU_386DX, 40000000, 1, 0, 0x0308, 0, 0, 0, 7,7,3,3, 5},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0}
};
CPU cpus_IBM386SLC[] = {
/*IBM 386SLC*/
{"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0, 0x300, 0, 0, 0, 3,3,3,3, 2},
{"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0, 0x300, 0, 0, 0, 4,4,3,3, 3},
{"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0, 0x300, 0, 0, 0, 4,4,3,3, 3},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0}
};
CPU cpus_IBM486SLC[] = {
/*IBM 486SLC*/
{"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
{"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 6},
{"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 7},
{"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
{"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0}
};
CPU cpus_IBM486BL[] = {
/*IBM Blue Lightning*/
{"486BL2/50", CPU_IBM486BL, 50000000, 2, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6, 6},
{"486BL2/66", CPU_IBM486BL, 66666666, 2, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"486BL3/75", CPU_IBM486BL, 75000000, 3, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
{"486BL3/100", CPU_IBM486BL, 100000000, 3, 0, 0x400, 0, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0}
};
CPU cpus_486SLC[] = {
/*Cx486SLC*/
{"Cx486SLC/20", CPU_486SLC, 20000000, 1, 0, 0x400, 0, 0x0000, 0, 4,4,3,3, 3},

4
src/cpu/x86_ops_mov_ctrl.h
View File

@@ -127,7 +127,9 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat)
mmu_perm=4;
if (is486 && !(cr0 & (1 << 30)))
cpu_cache_int_enabled = 1;
else
else if (isibmcpu)
cpu_cache_int_enabled = 1;
else
cpu_cache_int_enabled = 0;
if (is486 && ((cr0 ^ old_cr0) & (1 << 30)))
cpu_update_waitstates();