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Redid the SCAT ROMCS handling again (required changes in mem.c/h), fixes #435.

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This commit is contained in:
OBattler
2019-10-19 01:24:42 +02:00
parent 544eb0f1c9
commit 4f2cdf3b39
13 changed files with 129 additions and 130 deletions
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18
src/chipset/acc2168.c
View File

@@ -9,7 +9,7 @@
* Implementation of the ACC 2168 chipset
* used by the Packard Bell Legend 760 Supreme (PB410A or PB430).
*
* Version: @(#)acc2168.c 1.0.0 2019/05/13
* Version: @(#)acc2168.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
*
@@ -50,38 +50,38 @@ acc2168_shadow_recalc(acc2168_t *dev)
if (dev->regs[0x02] & 8) {
switch (dev->regs[0x02] & 0x30) {
case 0x00:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x10:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x30:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (dev->regs[0x02] & 4) {
switch (dev->regs[0x02] & 0x30) {
case 0x00:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x10:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x30:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}

8
src/chipset/ali1429.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the ALi M-1429/1431 chipset.
*
* Version: @(#)ali1429.c 1.0.8 2019/04/08
* Version: @(#)ali1429.c 1.0.9 2019/10/09
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -59,11 +59,11 @@ ali1429_recalc(ali1429_t *dev)
if (dev->regs[0x13] & (1 << i)) {
shadowbios |= (base >= 0xe8000) && !!(dev->regs[0x14] & 0x01);
shadowbios_write |= (base >= 0xe8000) && !!(dev->regs[0x14] & 0x02);
shflags = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
shflags |= !(dev->regs[0x14] & 0x02) ? MEM_WRITE_EXTERNAL : MEM_WRITE_INTERNAL;
shflags = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= !(dev->regs[0x14] & 0x02) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
flushmmucache();

14
src/chipset/headland.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the HEADLAND AT286 chipset.
*
* Version: @(#)headland.c 1.0.0 2019/05/14
* Version: @(#)headland.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -17,8 +17,8 @@
*
* Copyright 2010-2019 Sarah Walker.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2017,2018 Miran Grca.
* Copyright 2017,2018 GreatPsycho.
* Copyright 2017-2019 Miran Grca.
* Copyright 2017-2019 GreatPsycho.
*/
#include <stdio.h>
#include <stdint.h>
@@ -176,7 +176,7 @@ memmap_state_update(headland_t *dev)
addr = get_addr(dev, 0x40000 + (i << 14), NULL);
mem_mapping_set_exec(&dev->upper_mapping[i], addr < ((uint32_t)mem_size << 10) ? ram + addr : NULL);
}
mem_set_mem_state(0xA0000, 0x40000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xA0000, 0x40000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
if (mem_size > 640) {
if ((dev->cr[0] & 4) == 0) {
mem_mapping_set_addr(&dev->mid_mapping, 0x100000, mem_size > 1024 ? 0x60000 : (mem_size - 640) << 10);
@@ -222,7 +222,7 @@ hl_write(uint16_t addr, uint8_t val, void *priv)
if (shadowbios)
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
} else if (dev->indx == 0x87) {
if ((val & 1) && !(old_val & 1))
softresetx86();
@@ -263,8 +263,8 @@ hl_write(uint16_t addr, uint8_t val, void *priv)
switch(dev->cri) {
case 0:
dev->cr[0] = (val & 0x1f) | mem_conf_cr0[(mem_size > 640 ? mem_size : mem_size - 128) >> 9];
mem_set_mem_state(0xe0000, 0x10000, (val & 8 ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
mem_set_mem_state(0xf0000, 0x10000, (val & 0x10 ? MEM_READ_INTERNAL: MEM_READ_EXTERNAL) | MEM_WRITE_DISABLED);
mem_set_mem_state(0xe0000, 0x10000, (val & 8 ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | MEM_WRITE_DISABLED);
mem_set_mem_state(0xf0000, 0x10000, (val & 0x10 ? MEM_READ_INTERNAL: MEM_READ_EXTANY) | MEM_WRITE_DISABLED);
memmap_state_update(dev);
break;

8
src/chipset/intel_4x0.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Intel PCISet chips from 420TX to 440FX.
*
* Version: @(#)intel_4x0.c 1.0.0 2019/05/13
* Version: @(#)intel_4x0.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -54,13 +54,13 @@ i4x0_map(uint32_t addr, uint32_t size, int state)
{
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);

2
src/chipset/opti495.c
View File

@@ -298,7 +298,7 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
if (!(val & 0x80))
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
}
}
break;

11
src/chipset/scat.c
View File

@@ -10,7 +10,7 @@
*
* Re-worked version based on the 82C235 datasheet and errata.
*
* Version: @(#)scat.c 1.0.0 2019/05/13
* Version: @(#)scat.c 1.0.1 2019/10/19
*
* Authors: Original by GreatPsycho for PCem.
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -126,7 +126,7 @@ shadow_state_update(scat_t *dev)
{
int i, val;
uint32_t base, bit, romcs, rommap_r, rommap_w, wp, shflags = 0;
uint32_t base, bit, romcs, wp, shflags = 0;
for (i = 0; i < 24; i++) {
val = (dev->regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1;
@@ -142,15 +142,12 @@ shadow_state_update(scat_t *dev)
wp = dev->regs[SCAT_RAM_WRITE_PROTECT] & (1 << bit);
}
rommap_r = mem_mapping_is_romcs(base, 0) ? romcs : 1;
rommap_w = mem_mapping_is_romcs(base, 1) ? romcs : 1;
shflags = val ? MEM_READ_INTERNAL : (rommap_r ? MEM_READ_EXTERNAL : MEM_READ_DISABLED);
shflags = val ? MEM_READ_INTERNAL : (romcs ? MEM_READ_ROMCS : MEM_READ_EXTERNAL);
if (wp)
shflags |= MEM_WRITE_DISABLED;
else
shflags |= (val ? MEM_WRITE_INTERNAL : (rommap_w ? MEM_WRITE_EXTERNAL : MEM_WRITE_DISABLED));
shflags |= (val ? MEM_WRITE_INTERNAL : (romcs ? MEM_WRITE_ROMCS : MEM_WRITE_EXTERNAL));
mem_set_mem_state(base, 0x4000, shflags);
}

10
src/chipset/sis_85c471.c
View File

@@ -11,7 +11,7 @@
* SiS sis85c471 Super I/O Chip
* Used by DTK PKM-0038S E-2
*
* Version: @(#)sis_85c471.c 1.0.0 2019/05/13
* Version: @(#)sis_85c471.c 1.0.1 2019/10/19
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <http://pcem-emulator.co.uk/>
@@ -63,11 +63,11 @@ sis_85c471_recalcmapping(sis_85c471_t *dev)
if ((i > 5) || (dev->regs[0x02] & (1 << i))) {
shadowbios |= (base >= 0xe0000) && (dev->regs[0x02] & 0x80);
shadowbios_write |= (base >= 0xe0000) && !(dev->regs[0x02] & 0x40);
shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
shflags |= (dev->regs[0x02] & 0x40) ? MEM_WRITE_EXTERNAL : MEM_WRITE_INTERNAL;
shflags = (dev->regs[0x02] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x02] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTERNAL);
}
flushmmucache();
@@ -125,7 +125,7 @@ sis_85c471_write(uint16_t port, uint8_t val, void *priv)
if (dev->regs[0x13] & 0x10)
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
break;

10
src/chipset/sis_85c496.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the SiS 85c496/85c497 chip.
*
* Version: @(#)sis_85c496.c 1.0.0 2019/05/13
* Version: @(#)sis_85c496.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -96,11 +96,11 @@ sis_85c496_recalcmapping(sis_85c496_t *dev)
if (dev->pci_conf[0x44] & (1 << i)) {
shadowbios |= (base >= 0xe0000) && (dev->pci_conf[0x45] & 0x02);
shadowbios_write |= (base >= 0xe0000) && !(dev->pci_conf[0x45] & 0x01);
shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTERNAL : MEM_WRITE_INTERNAL;
shflags = (dev->pci_conf[0x45] & 0x02) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->pci_conf[0x45] & 0x01) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL;
mem_set_mem_state(base, 0x8000, shflags);
} else
mem_set_mem_state(base, 0x8000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
flushmmucache();
@@ -185,7 +185,7 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
if (val & 0x04)
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
else
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
break;

10
src/chipset/sis_85c50x.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the SiS 85c501/85c503 chip.
*
* Version: @(#)sis_85c50x.c 1.0.0 2019/05/13
* Version: @(#)sis_85c50x.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -59,20 +59,20 @@ sis_85c501_recalcmapping(sis_85c50x_t *dev)
if (dev->pci_conf[0][0x54 + c] & (1 << (d + 4))) {
switch (dev->pci_conf[0][0x53] & 0x60) {
case 0x00:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 0x20:
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x40:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
case 0x60:
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
}
} else
mem_set_mem_state(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}

8
src/chipset/wd76c10.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the WD76C10 System Controller chip.
*
* Version: @(#)wd76c10.c 1.0.0 2019/05/14
* Version: @(#)wd76c10.c 1.0.1 2019/10/19
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -135,13 +135,13 @@ wd76c10_write(uint16_t port, uint16_t val, void *priv)
dev->reg_f872 = val;
switch (val & 3) {
case 0:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xd0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);

79
src/mem.c
View File

@@ -12,7 +12,7 @@
* the DYNAMIC_TABLES=1 enables this. Will eventually go
* away, either way...
*
* Version: @(#)mem.c 1.0.20 2019/03/24
* Version: @(#)mem.c 1.0.21 2019/10/19
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -861,51 +861,6 @@ mem_mapping_is_romcs(uint32_t addr, int write)
return 0;
}
#if 0
uint8_t
mem_readb_phys(uint32_t addr)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
if (_mem_exec[addr >> MEM_GRANULARITY_BITS])
return _mem_exec[addr >> MEM_GRANULARITY_BITS][addr & MEM_GRANULARITY_MASK];
else if (map && map->read_b)
return map->read_b(addr, map->p);
else
return 0xff;
}
uint16_t
mem_readw_phys(uint32_t addr)
{
mem_mapping_t *map = read_mapping[addr >> MEM_GRANULARITY_BITS];
uint16_t temp;
if (_mem_exec[addr >> MEM_GRANULARITY_BITS])
return ((uint16_t *) _mem_exec[addr >> MEM_GRANULARITY_BITS])[(addr >> 1) & MEM_GRANULARITY_HMASK];
else if (map && map->read_w)
return map->read_w(addr, map->p);
else {
temp = mem_readb_phys(addr + 1) << 8;
temp |= mem_readb_phys(addr);
}
return temp;
}
void
mem_writeb_phys(uint32_t addr, uint8_t val)
{
mem_mapping_t *map = write_mapping[addr >> MEM_GRANULARITY_BITS];
if (_mem_exec[addr >> MEM_GRANULARITY_BITS])
_mem_exec[addr >> MEM_GRANULARITY_BITS][addr & MEM_GRANULARITY_MASK] = val;
else if (map && map->write_b)
map->write_b(addr, val, map->p);
}
uint8_t
mem_readb_phys(uint32_t addr)
@@ -944,7 +899,6 @@ mem_writeb_phys(uint32_t addr, uint8_t val)
if (map && map->write_b)
map->write_b(addr, val, map->p);
}
}
@@ -1199,7 +1153,16 @@ mem_mapping_read_allowed(uint32_t flags, int state)
case MEM_READ_ANY:
return 1;
/* On external and 0 mappings without ROMCS. */
case MEM_READ_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS);
/* On external and 0 mappings with ROMCS. */
case MEM_READ_ROMCS:
return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS);
/* On any external mappings. */
case MEM_READ_EXTANY:
return !(flags & MEM_MAPPING_INTERNAL);
@@ -1219,12 +1182,25 @@ mem_mapping_write_allowed(uint32_t flags, int state)
{
switch (state & MEM_WRITE_MASK) {
case MEM_WRITE_DISABLED:
return 0;
case MEM_WRITE_ANY:
return 1;
/* On external and 0 mappings without ROMCS. */
case MEM_WRITE_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS);
/* On external and 0 mappings with ROMCS. */
case MEM_WRITE_ROMCS:
return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS);
/* On any external mappings. */
case MEM_WRITE_EXTANY:
return !(flags & MEM_MAPPING_INTERNAL);
case MEM_WRITE_INTERNAL:
return !(flags & MEM_MAPPING_EXTERNAL);
default:
fatal("mem_mapping_write_allowed : bad state %x\n", state);
@@ -1438,11 +1414,17 @@ mem_add_bios(void)
mem_mapping_add(&bios_mapping, 0xe0000, 0x20000,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
&rom[0x20000], MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(0x0e0000, 0x20000,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else {
mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(biosaddr, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
@@ -1450,6 +1432,9 @@ mem_add_bios(void)
mem_mapping_add(&bios_high_mapping, biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
}

45
src/mem.h
View File

@@ -1,38 +1,22 @@
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the VARCem Project.
* This file is part of the 86Box distribution.
*
* Definitions for the memory interface.
*
* Version: @(#)mem.h 1.0.9 2019/02/11
* Version: @(#)mem.h 1.0.10 2019/10/19
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Sarah Walker, <tommowalker@tommowalker.co.uk>
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2017,2018 Fred N. van Kempen.
* Copyright 2008-2018 Sarah Walker.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
* Copyright 2008-2019 Sarah Walker.
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2016-2018 Miran Grca.
*/
#ifndef EMU_MEM_H
# define EMU_MEM_H
@@ -51,12 +35,16 @@
#define MEM_READ_INTERNAL 0x10
#define MEM_READ_EXTERNAL 0x20
#define MEM_READ_DISABLED 0x30
#define MEM_READ_ROMCS 0x60 /* EXTERNAL type + ROMC flag */
#define MEM_READ_EXTANY 0x70 /* Any EXTERNAL type */
#define MEM_READ_MASK 0xf0
#define MEM_WRITE_ANY 0x00
#define MEM_WRITE_INTERNAL 0x01
#define MEM_WRITE_EXTERNAL 0x02
#define MEM_WRITE_DISABLED 0x03
#define MEM_WRITE_ROMCS 0x06 /* EXTERNAL type + ROMC flag */
#define MEM_WRITE_EXTANY 0x07 /* Any EXTERNAL type */
#define MEM_WRITE_MASK 0x0f
/* #define's for memory granularity, currently 16k, but may
@@ -272,7 +260,6 @@ extern void mem_mapping_set_addr(mem_mapping_t *,
extern void mem_mapping_set_exec(mem_mapping_t *, uint8_t *exec);
extern void mem_mapping_disable(mem_mapping_t *);
extern void mem_mapping_enable(mem_mapping_t *);
extern int mem_mapping_is_romcs(uint32_t addr, int write);
extern void mem_set_mem_state(uint32_t base, uint32_t size, int state);

36
src/mem_new.c
View File

@@ -12,7 +12,7 @@
* the DYNAMIC_TABLES=1 enables this. Will eventually go
* away, either way...
*
* Version: @(#)mem.c 1.0.20 2019/03/24
* Version: @(#)mem.c 1.0.21 2019/10/19
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
@@ -1194,7 +1194,16 @@ mem_mapping_read_allowed(uint32_t flags, int state)
case MEM_READ_ANY:
return 1;
/* On external and 0 mappings without ROMCS. */
case MEM_READ_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS);
/* On external and 0 mappings with ROMCS. */
case MEM_READ_ROMCS:
return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS);
/* On any external mappings. */
case MEM_READ_EXTANY:
return !(flags & MEM_MAPPING_INTERNAL);
case MEM_READ_INTERNAL:
@@ -1214,12 +1223,25 @@ mem_mapping_write_allowed(uint32_t flags, int state)
switch (state & MEM_WRITE_MASK) {
case MEM_WRITE_DISABLED:
return 0;
case MEM_WRITE_ANY:
return 1;
/* On external and 0 mappings without ROMCS. */
case MEM_WRITE_EXTERNAL:
return !(flags & MEM_MAPPING_INTERNAL) && !(flags & MEM_MAPPING_ROMCS);
/* On external and 0 mappings with ROMCS. */
case MEM_WRITE_ROMCS:
return !(flags & MEM_MAPPING_INTERNAL) && (flags & MEM_MAPPING_ROMCS);
/* On any external mappings. */
case MEM_WRITE_EXTANY:
return !(flags & MEM_MAPPING_INTERNAL);
case MEM_WRITE_INTERNAL:
return !(flags & MEM_MAPPING_EXTERNAL);
default:
fatal("mem_mapping_write_allowed : bad state %x\n", state);
}
@@ -1433,19 +1455,27 @@ mem_add_bios(void)
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
&rom[0x20000], MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(0x0e0000, 0x20000,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
} else {
mem_mapping_add(&bios_mapping, biosaddr, biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(biosaddr, biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
if (AT) {
mem_mapping_add(&bios_high_mapping, biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
mem_read_bios,mem_read_biosw,mem_read_biosl,
mem_write_null,mem_write_nullw,mem_write_nulll,
rom,
MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
rom, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROM|MEM_MAPPING_ROMCS, 0);
mem_set_mem_state(biosaddr | (cpu_16bitbus ? 0x00f00000 : 0xfff00000), biosmask + 1,
MEM_READ_ROMCS | MEM_WRITE_ROMCS);
}
}