Improved the VIA VPX code
Moved host bridge write code via_vpx_write. Default registers are now on via_vpx_init. Read only registers are hardcoded.
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tiseno100
GitHub
@@ -12,6 +12,9 @@ VIA Apollo VPX North Bridge emulation
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VT82C585VPX used in the Zida Tomato TX100 board
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based on the model of VIA MVP3 by mooch & Sarah
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There's also a SOYO board using the ETEQ chipset which is a rebranded
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VPX + 586B but fails to save on CMOS properly.
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Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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Copyright(C) 2020 Tiseno100
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Copyright(C) 2020 Melissa Goad
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@@ -35,7 +38,7 @@ Copyright(C) 2020 Miran Grca
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typedef struct via_vpx_t
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{
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uint8_t pci_conf[2][256];
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uint8_t pci_conf[256];
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} via_vpx_t;
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static void
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@@ -60,109 +63,63 @@ vpx_map(uint32_t addr, uint32_t size, int state)
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}
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static void
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via_vpx_pci_regs(via_vpx_t *dev)
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{
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memset(dev, 0, sizeof(via_vpx_t));
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// Host Bridge registers
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dev->pci_conf[0][0x00] = 0x06; // VIA
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dev->pci_conf[0][0x01] = 0x11;
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dev->pci_conf[0][0x02] = 0x85; // VT82C585VPX
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dev->pci_conf[0][0x03] = 0x05;
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dev->pci_conf[0][0x04] = 7; // Command
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dev->pci_conf[0][0x05] = 0;
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dev->pci_conf[0][0x06] = 0xa0; // Status
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dev->pci_conf[0][0x07] = 2;
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dev->pci_conf[0][0x09] = 0; // Program Interface
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dev->pci_conf[0][0x0a] = 0; // Sub Class Code
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dev->pci_conf[0][0x0b] = 6; // Base Class Code
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dev->pci_conf[0][0x0c] = 0; // reserved
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dev->pci_conf[0][0x0d] = 0; // Latency Timer
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dev->pci_conf[0][0x0e] = 0; // Header Type
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dev->pci_conf[0][0x0f] = 0; // Built-in Self test
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dev->pci_conf[0][0x58] = 0x40; // DRAM Configuration 1
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dev->pci_conf[0][0x59] = 5; // DRAM Configuration 2
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dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending
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dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending
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dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending
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dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending
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dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending
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dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending
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dev->pci_conf[0][0x64] = 0xab; // DRAM reference timing
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}
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static void
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host_bridge_write(int func, int addr, uint8_t val, void *priv)
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via_vpx_write(int func, int addr, uint8_t val, void *priv)
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{
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via_vpx_t *dev = (via_vpx_t *) priv;
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// Read-Only registers. Exact same as MVP3
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if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) ||
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((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) ||
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((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd)))
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return;
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// Read-Only registers
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switch(addr){
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case 0x00: case 0x01: case 0x02: case 0x03:
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case 0x08: case 0x09: case 0x0a: case 0x0b:
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case 0x0e: case 0x0f:
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return;
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}
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switch(addr){
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case 0x04: // Command
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dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
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case 0x04: // Command. On Bitfield 6 RW
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dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40);
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case 0x07: // Status
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dev->pci_conf[0][0x07] &= ~(val & 0xb0);
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dev->pci_conf[0x07] &= ~(val & 0xb0);
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break;
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case 0x61: // Shadow RAM control 1
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if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
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if ((dev->pci_conf[0x61] ^ val) & 0x03)
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vpx_map(0xc0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
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if ((dev->pci_conf[0x61] ^ val) & 0x0c)
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vpx_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
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if ((dev->pci_conf[0x61] ^ val) & 0x30)
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vpx_map(0xc8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
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if ((dev->pci_conf[0x61] ^ val) & 0xc0)
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vpx_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x61] = val;
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dev->pci_conf[0x61] = val;
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return;
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case 0x62: // Shadow RAM Control 2
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if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
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if ((dev->pci_conf[0x62] ^ val) & 0x03)
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vpx_map(0xd0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
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if ((dev->pci_conf[0x62] ^ val) & 0x0c)
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vpx_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
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if ((dev->pci_conf[0x62] ^ val) & 0x30)
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vpx_map(0xd8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
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if ((dev->pci_conf[0x62] ^ val) & 0xc0)
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vpx_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x62] = val;
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dev->pci_conf[0x62] = val;
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return;
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case 0x63: // Shadow RAM Control 3
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if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
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if ((dev->pci_conf[0x63] ^ val) & 0x30) {
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vpx_map(0xf0000, 0x10000, (val & 0x30) >> 4);
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shadowbios = (((val & 0x30) >> 4) & 0x02);
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}
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if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
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if ((dev->pci_conf[0x63] ^ val) & 0xc0)
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vpx_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x63] = val;
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dev->pci_conf[0x63] = val;
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return;
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//In case we throw somewhere
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default:
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dev->pci_conf[0][addr] = val;
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dev->pci_conf[addr] = val;
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break;
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}
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}
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@@ -175,19 +132,13 @@ via_vpx_read(int func, int addr, void *priv)
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switch(func) {
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case 0:
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ret = dev->pci_conf[0][addr];
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ret = dev->pci_conf[addr];
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break;
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}
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return ret;
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}
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static void
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via_vpx_write(int func, int addr, uint8_t val, void *priv)
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{
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host_bridge_write(func, addr, val, priv);
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}
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static void
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via_vpx_reset(void *priv)
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{
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@@ -198,10 +149,47 @@ static void *
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via_vpx_init(const device_t *info)
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{
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via_vpx_t *dev = (via_vpx_t *) malloc(sizeof(via_vpx_t));
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memset(dev, 0, sizeof(via_vpx_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, via_vpx_read, via_vpx_write, dev);
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via_vpx_pci_regs(dev);
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dev->pci_conf[0x00] = 0x06; // VIA
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dev->pci_conf[0x01] = 0x11;
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dev->pci_conf[0x02] = 0x85; // VT82C585VPX
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dev->pci_conf[0x03] = 0x05;
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dev->pci_conf[0x04] = 7; // Command
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dev->pci_conf[0x05] = 0;
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dev->pci_conf[0x06] = 0xa0; // Status
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dev->pci_conf[0x07] = 2;
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dev->pci_conf[0x09] = 0; // Program Interface
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dev->pci_conf[0x0a] = 0; // Sub Class Code
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dev->pci_conf[0x0b] = 6; // Base Class Code
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dev->pci_conf[0x0c] = 0; // reserved
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dev->pci_conf[0x0d] = 0; // Latency Timer
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dev->pci_conf[0x0e] = 0; // Header Type
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dev->pci_conf[0x0f] = 0; // Built-in Self test
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dev->pci_conf[0x58] = 0x40; // DRAM Configuration 1
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dev->pci_conf[0x59] = 0x05; // DRAM Configuration 2
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dev->pci_conf[0x5a] = 1; // Bank 0 Ending
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dev->pci_conf[0x5b] = 1; // Bank 1 Ending
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dev->pci_conf[0x5c] = 1; // Bank 2 Ending
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dev->pci_conf[0x5d] = 1; // Bank 3 Ending
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dev->pci_conf[0x5e] = 1; // Bank 4 Ending
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dev->pci_conf[0x5f] = 1; // Bank 5 Ending
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dev->pci_conf[0x64] = 0xab; // DRAM reference timing
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return dev;
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}
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