Implemented the OPTi 822 VLB to PCI bridge
Needed for early OPTi Pentium's but also 486's like the Packard Bell PB450 PCI. IRQ routing is hacking though!!
This commit is contained in:
@@ -32,32 +32,6 @@
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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/* Shadow RAM */
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/* Register 4h: C0000-CFFFF range | Register 5h: D0000-DFFFF range */
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#define CURRENT_REGISTER dev->regs[4 + !!(i & 4)]
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/*
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Bits 7-6: xC000-xFFFF
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Bits 5-4: x8000-xBFFF
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Bits 3-2: x4000-x7FFF
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Bits 0-1: x0000-x3FFF
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x-y
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0 0 Read/Write AT bus
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1 0 Read from AT - Write to DRAM
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1 1 Read from DRAM - Write to DRAM
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0 1 Read from DRAM (write protected)
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*/
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#define CAN_READ (1 << (i - (4 * !!(i & 4))) * 2)
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#define CAN_WRITE (1 << ((i - (4 * !!(i & 4))) * 2 + 1))
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/* Shadow Recalc for the C/D segments */
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#define SHADOW_RECALC (((CURRENT_REGISTER & CAN_READ) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((CURRENT_REGISTER & CAN_WRITE) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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/* Shadow Recalc for the E/F segments */
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#define SHADOW_EF_RECALC (((dev->regs[6] & CAN_READ) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & CAN_WRITE) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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typedef struct
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{
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uint8_t idx, regs[16];
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@@ -83,17 +57,36 @@ opti5x7_log(const char *fmt, ...)
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#endif
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static void
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shadow_map(opti5x7_t *dev)
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opti5x7_shadow_map(int cur_reg, opti5x7_t *dev)
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{
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for (int i = 0; i < 8; i++)
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/*
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Register 4h: Cxxxx Segment
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Register 5h: Dxxxx Segment
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Bits 7-6: xC000-xFFFF
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Bits 5-4: x8000-xBFFF
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Bits 3-2: x4000-x7FFF
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Bits 0-1: x0000-x3FFF
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x-y
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0 0 Read/Write AT bus
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1 0 Read from AT - Write to DRAM
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1 1 Read from DRAM - Write to DRAM
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0 1 Read from DRAM (write protected)
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*/
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if (cur_reg == 0x06)
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{
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, SHADOW_RECALC);
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if (i < 2)
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mem_set_mem_state_both(0xe0000 + (i << 16), 0x10000, SHADOW_EF_RECALC);
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mem_set_mem_state_both(0xe0000, 0x10000, ((dev->regs[6] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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}
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shadowbios = !!(dev->regs[0x06] & 5);
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shadowbios_write = !!(dev->regs[0x06] & 0x0a);
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flushmmucache();
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else
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{
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for (int i = 0; i < 4; i++)
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mem_set_mem_state_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
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}
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flushmmucache_nopc();
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}
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static void
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@@ -107,7 +100,6 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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dev->idx = val;
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break;
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case 0x24:
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opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, val);
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switch (dev->idx)
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{
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case 0x00: /* DRAM Configuration Register #1 */
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@@ -116,7 +108,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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case 0x01: /* DRAM Control Register #1 */
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dev->regs[dev->idx] = val;
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break;
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case 0x02: /* Cache Control Register #1 */
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case 0x02: /* Cache Control Register #1 */
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dev->regs[dev->idx] = val;
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c);
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cpu_update_waitstates();
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@@ -128,7 +120,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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case 0x05: /* Shadow RAM Control Register #2 */
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case 0x06: /* Shadow RAM Control Register #3 */
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dev->regs[dev->idx] = val;
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shadow_map(dev);
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opti5x7_shadow_map(dev->idx, dev);
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break;
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case 0x07: /* Tag Test Register */
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case 0x08: /* CPU Cache Control Register #1 */
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@@ -148,6 +140,7 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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dev->regs[dev->idx] = val;
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break;
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}
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opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]);
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break;
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}
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}
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322
src/chipset/opti822.c
Normal file
322
src/chipset/opti822.c
Normal file
@@ -0,0 +1,322 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C822 VESA Local Bus to PCI Bridge Interface.
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*
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*
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* Authors: Tiseno100,
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*
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* Copyright 2021 Tiseno100.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/chipset.h>
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/* Shadow RAM */
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#define SYSTEM_READ ((dev->pci_conf[0x44] & 2) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
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#define SYSTEM_WRITE ((dev->pci_conf[0x44] & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
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#define SHADOW_READ ((dev->pci_conf[cur_reg] & (1 << (4 + i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
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#define SHADOW_WRITE ((dev->pci_conf[cur_reg] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)
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#ifdef ENABLE_OPTI822_LOG
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int opti822_do_log = ENABLE_OPTI822_LOG;
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static void
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opti822_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti822_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define opti822_log(fmt, ...)
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#endif
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typedef struct opti822_t
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{
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uint8_t pci_conf[256];
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} opti822_t;
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int opti822_irq_routing[7] = {5, 9, 0x0a, 0x0b, 0x0c, 0x0e, 0x0f};
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void opti822_shadow(int cur_reg, opti822_t *dev)
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{
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if (cur_reg == 0x44)
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mem_set_mem_state_both(0xf0000, 0x10000, SYSTEM_READ | SYSTEM_WRITE);
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else
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for (int i = 0; i < 4; i++)
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mem_set_mem_state_both(0xe0000 - (((cur_reg & 3) - 1) << 16) + (i << 14), 0x4000, SHADOW_READ | SHADOW_WRITE);
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flushmmucache_nopc();
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}
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static void
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opti822_write(int func, int addr, uint8_t val, void *priv)
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{
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opti822_t *dev = (opti822_t *)priv;
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switch (func)
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{
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case 0x04: /* Command Register */
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dev->pci_conf[addr] = val & 0x40;
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break;
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case 0x05: /* Command Register */
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dev->pci_conf[addr] = val & 1;
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break;
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case 0x06: /* Status Register */
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dev->pci_conf[addr] |= val & 0xc0;
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break;
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case 0x07: /* Status Register */
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dev->pci_conf[addr] = val & 0xa9;
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break;
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case 0x40:
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dev->pci_conf[addr] = val & 0xc0;
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break;
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case 0x41:
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dev->pci_conf[addr] = val & 0xcf;
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break;
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case 0x42:
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dev->pci_conf[addr] = val & 0xf8;
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break;
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case 0x43:
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dev->pci_conf[addr] = val;
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break;
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case 0x44: /* Shadow RAM */
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case 0x45:
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case 0x46:
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case 0x47:
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dev->pci_conf[addr] = (addr == 0x44) ? (val & 0xcb) : val;
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opti822_shadow(addr, dev);
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break;
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case 0x48:
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case 0x49:
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case 0x4a:
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case 0x4b:
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case 0x4c:
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case 0x4d:
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case 0x4e:
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case 0x4f:
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case 0x50:
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case 0x51:
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case 0x52:
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case 0x53:
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case 0x54:
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case 0x55:
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case 0x56:
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case 0x57:
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dev->pci_conf[addr] = val;
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break;
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case 0x58:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x59:
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case 0x5a:
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case 0x5b:
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case 0x5c:
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case 0x5d:
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case 0x5e:
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case 0x5f:
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dev->pci_conf[addr] = val;
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break;
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case 0x60:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x61:
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case 0x62:
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case 0x63:
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case 0x64:
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case 0x65:
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case 0x66:
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case 0x67:
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dev->pci_conf[addr] = val;
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break;
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case 0x68:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x69:
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case 0x6a:
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case 0x6b:
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case 0x6c:
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case 0x6d:
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case 0x6e:
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case 0x6f:
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dev->pci_conf[addr] = val;
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break;
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case 0x70:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x71:
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case 0x72:
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case 0x73:
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dev->pci_conf[addr] = val;
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break;
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case 0x74:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x75:
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case 0x76:
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dev->pci_conf[addr] = val;
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break;
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case 0x77:
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dev->pci_conf[addr] = val & 0xe7;
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break;
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case 0x78:
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dev->pci_conf[addr] = val;
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break;
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case 0x79:
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dev->pci_conf[addr] = val & 0xfc;
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break;
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case 0x7a:
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case 0x7b:
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case 0x7c:
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case 0x7d:
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case 0x7e:
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dev->pci_conf[addr] = val;
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break;
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case 0x7f:
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dev->pci_conf[addr] = val & 3;
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break;
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x84:
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case 0x85:
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case 0x86:
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dev->pci_conf[addr] = val;
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break;
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case 0x88: /* PCI IRQ Routing */
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case 0x89: /* Very hacky implementation. Needs surely a rewrite after */
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case 0x8a: /* a PCI rework happens. */
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case 0x8b:
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case 0x8c:
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case 0x8d:
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case 0x8e:
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case 0x8f:
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dev->pci_conf[addr] = val;
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if (addr % 2)
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{
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pci_set_irq_routing(PCI_INTB, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTA, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED);
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}
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else
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{
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pci_set_irq_routing(PCI_INTD, ((val & 0x0f) != 0) ? opti822_irq_routing[(val & 7) - 1] : PCI_IRQ_DISABLED);
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pci_set_irq_routing(PCI_INTC, (((val >> 4) & 0x0f) != 0) ? opti822_irq_routing[((val >> 4) & 7) - 1] : PCI_IRQ_DISABLED);
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}
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break;
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}
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opti822_log("OPTI822: dev->pci_conf[%02x] = %02x\n", addr, dev->pci_conf[addr]);
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}
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static uint8_t
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opti822_read(int func, int addr, void *priv)
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{
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opti822_t *dev = (opti822_t *)priv;
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return dev->pci_conf[addr];
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}
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static void
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opti822_reset(void *priv)
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{
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opti822_t *dev = (opti822_t *)priv;
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dev->pci_conf[0x00] = 0x45;
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dev->pci_conf[0x01] = 0x10;
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dev->pci_conf[0x02] = 0x22;
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dev->pci_conf[0x03] = 0xc8;
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dev->pci_conf[0x04] = 7;
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dev->pci_conf[0x06] = 0x40;
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dev->pci_conf[0x07] = 1;
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dev->pci_conf[0x08] = 1;
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dev->pci_conf[0x0b] = 6;
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dev->pci_conf[0x0d] = 0x20;
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dev->pci_conf[0x40] = 1;
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dev->pci_conf[0x43] = 0x20;
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dev->pci_conf[0x52] = 6;
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dev->pci_conf[0x53] = 0x90;
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}
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static void
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opti822_close(void *priv)
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{
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opti822_t *dev = (opti822_t *)priv;
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free(dev);
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}
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static void *
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opti822_init(const device_t *info)
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{
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opti822_t *dev = (opti822_t *)malloc(sizeof(opti822_t));
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memset(dev, 0, sizeof(opti822_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_read, opti822_write, dev);
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opti822_reset(dev);
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return dev;
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}
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const device_t opti822_device = {
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"OPTi 82C822 PCIB",
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DEVICE_PCI,
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0,
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opti822_init,
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opti822_close,
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opti822_reset,
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{NULL},
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NULL,
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NULL,
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NULL};
|
@@ -97,7 +97,9 @@ extern const device_t opti291_device;
|
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extern const device_t opti493_device;
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extern const device_t opti495_device;
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extern const device_t opti802g_device;
|
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extern const device_t opti822_device;
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extern const device_t opti895_device;
|
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|
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extern const device_t opti5x7_device;
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/* SiS */
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|
@@ -380,6 +380,9 @@ extern const device_t *at_cpqiii_get_device(void);
|
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/* m_at_socket4_5.c */
|
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extern int machine_at_excalibur_init(const machine_t *);
|
||||
|
||||
extern int machine_at_hot543_init(const machine_t *);
|
||||
extern int machine_at_p54vl_init(const machine_t *);
|
||||
|
||||
extern int machine_at_batman_init(const machine_t *);
|
||||
extern int machine_at_ambradp60_init(const machine_t *);
|
||||
extern int machine_at_dellxp60_init(const machine_t *);
|
||||
|
@@ -63,6 +63,61 @@ machine_at_excalibur_init(const machine_t *model)
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
machine_at_hot543_init(const machine_t *model)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = bios_load_linear("roms/machines/hot543/543_R21.BIN",
|
||||
0x000e0000, 131072, 0);
|
||||
|
||||
if (bios_only || !ret)
|
||||
return ret;
|
||||
|
||||
machine_at_common_init(model);
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
||||
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
device_add(&opti5x7_device);
|
||||
device_add(&opti822_device);
|
||||
device_add(&sst_flash_29ee010_device);
|
||||
device_add(&keyboard_at_device);
|
||||
|
||||
if (fdc_type == FDC_INTERNAL)
|
||||
device_add(&fdc_at_device);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
machine_at_p54vl_init(const machine_t *model)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = bios_load_linear("roms/machines/p54vl/SM507.ROM",
|
||||
0x000e0000, 131072, 0);
|
||||
|
||||
if (bios_only || !ret)
|
||||
return ret;
|
||||
|
||||
machine_at_common_init(model);
|
||||
pci_init(PCI_CONFIG_TYPE_1);
|
||||
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
|
||||
pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4);
|
||||
pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1);
|
||||
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
|
||||
device_add(&opti5x7_device);
|
||||
device_add(&opti822_device);
|
||||
device_add(&sst_flash_29ee010_device);
|
||||
device_add(&keyboard_at_ami_device);
|
||||
|
||||
if (fdc_type == FDC_INTERNAL)
|
||||
device_add(&fdc_at_device);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void
|
||||
machine_at_premiere_common_init(const machine_t *model, int pci_switch)
|
||||
|
@@ -282,6 +282,10 @@ const machine_t machines[] = {
|
||||
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_powermate_v_init, NULL },
|
||||
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
|
||||
|
||||
/* OPTi 596/597/822 */
|
||||
{ "[OPTi 597] Shuttle HOT-543", "hot543", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_hot543_init, NULL },
|
||||
{ "[OPTi 597] Supermicro P54VL-PCI", "p54vl", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_p54vl_init, NULL },
|
||||
|
||||
/* SiS 85C50x */
|
||||
{ "[SiS 85C50x] ASUS PCI/I-P54SP4", "p54sp4", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 40000000, 66666667, 3380, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p54sp4_init, NULL },
|
||||
{ "[SiS 85C50x] BCM SQ-588", "sq588", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_PENTIUMMMX), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_sq588_init, NULL },
|
||||
|
Reference in New Issue
Block a user