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Merge pull request #1198 from tiseno100/master

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Multiple machine & SIO implementations
This commit is contained in:
Miran Grča
2020-12-31 20:54:42 +01:00
committed by GitHub
parent dc5d3b9754 5d7ea72881
commit 62e89dbea9
10 changed files with 1053 additions and 3 deletions
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3
src/include/86box/machine.h
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@@ -309,6 +309,7 @@ extern int machine_at_vect486vl_init(const machine_t *);
extern int machine_at_403tg_init(const machine_t *);
extern int machine_at_pc330_6571_init(const machine_t *);
extern int machine_at_mvi486_init(const machine_t *);
extern int machine_at_sis401_init(const machine_t *);
extern int machine_at_av4_init(const machine_t *);
@@ -419,6 +420,7 @@ extern int machine_at_p65up5_cp55t2d_init(const machine_t *);
extern int machine_at_p55tvp4_init(const machine_t *);
extern int machine_at_p55va_init(const machine_t *);
extern int machine_at_i430vx_init(const machine_t *);
extern int machine_at_5ivg_init(const machine_t *);
extern int machine_at_brio80xx_init(const machine_t *);
extern int machine_at_8500tvxa_init(const machine_t *);
extern int machine_at_presario4500_init(const machine_t *);
@@ -489,6 +491,7 @@ extern int machine_at_ergox365_init(const machine_t *);
extern int machine_at_ficka6130_init(const machine_t *);
extern int machine_at_p3v133_init(const machine_t *);
extern int machine_at_p3v4x_init(const machine_t *);
extern int machine_at_vei8_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_tsunamiatx_get_device(void);

6
src/include/86box/sio.h
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@@ -32,6 +32,8 @@ extern const device_t fdc37c931apm_compaq_device;
extern const device_t fdc37c932fr_device;
extern const device_t fdc37c932qf_device;
extern const device_t fdc37c935_device;
extern const device_t fdc37m60x_device;
extern const device_t fdc37m60x_370_device;
extern const device_t i82091aa_device;
extern const device_t i82091aa_398_device;
extern const device_t i82091aa_ide_device;
@@ -41,9 +43,13 @@ extern const device_t pc87307_15c_device;
extern const device_t pc87307_both_device;
extern const device_t pc87309_device;
extern const device_t pc87309_15c_device;
extern const device_t pc87311_device;
extern const device_t pc87311_ide_device;
extern const device_t pc87332_device;
extern const device_t pc87332_ps1_device;
extern const device_t pc97307_device;
extern const device_t prime3c_device;
extern const device_t prime3c_ide_device;
extern const device_t ps1_m2133_sio;
extern const device_t sio_detect_device;
extern const device_t um8669f_device;

22
src/machine/m_at_386dx_486.c
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@@ -474,7 +474,6 @@ machine_at_opti495_mr_init(const machine_t *model)
return ret;
}
int
machine_at_403tg_init(const machine_t *model)
{
@@ -519,6 +518,27 @@ machine_at_pc330_6571_init(const machine_t *model) // doesn't like every CPU oth
return ret;
}
int
machine_at_mvi486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/mvi486/MVI627.BIN",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti895_device);
device_add(&keyboard_at_device);
device_add(&pc87311_ide_device);
return ret;
}
static void
machine_at_sis_85c471_common_init(const machine_t *model)
{

30
src/machine/m_at_slot1.c
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@@ -622,3 +622,33 @@ machine_at_p3v4x_init(const machine_t *model)
return ret;
}
int
machine_at_vei8_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/vei8/QHW1001.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4e_device);
device_add(&fdc37m60x_370_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 512);
return ret;
}

28
src/machine/m_at_socket7.c
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@@ -580,6 +580,34 @@ machine_at_p55tvp4_init(const machine_t *model)
return ret;
}
int
machine_at_5ivg_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/5ivg/5IVG.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x11, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x12, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_pci_device);
device_add(&prime3c_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_i430vx_init(const machine_t *model)
{

3
src/machine/machine_table.c
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@@ -200,6 +200,7 @@ const machine_t machines[] = {
{ "[OPTi 495] MR 486 clone", "mr486", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 32768, 1024, 127, machine_at_opti495_mr_init, NULL },
{ "[OPTi 802G] IBM PC 330 (type 6571)", "pc330_6571", MACHINE_TYPE_486, CPU_PKG_SOCKET3_PC330, 0, 25000000, 33333333, 0, 0, 2.0, 3.0, MACHINE_VLB | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_pc330_6571_init, NULL },
{ "[OPTi 895] Jetway J-403TG", "403tg", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB, 1024, 65536, 1024, 127, machine_at_403tg_init, NULL },
{ "[OPTi 895] Mylex MVI486", "mvi486", MACHINE_TYPE_486, CPU_PKG_SOCKET1, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE_DUAL, 1024, 65536, 1024, 127, machine_at_mvi486_init, NULL },
{ "[SiS 401] AMI 486 Clone", "sis401", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_sis401_init, NULL },
{ "[SiS 460] ABIT AV4", "av4", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_VLB | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_av4_init, NULL },
{ "[SiS 461] IBM PS/ValuePoint 433DX/Si", "valuepoint433", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_valuepoint433_init, NULL },
@@ -309,6 +310,7 @@ const machine_t machines[] = {
/* 430VX */
{ "[i430VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55tvp4_init, NULL },
{ "[i430VX] Azza 5IVG", "5ivg", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_5ivg_init, NULL },
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_8500tvxa_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55va_init, NULL },
@@ -373,6 +375,7 @@ const machine_t machines[] = {
{ "[i440BX] ABIT BF6", "bf6", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 133333333, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_bf6_init, NULL },
{ "[i440BX] AOpen AX6BC", "ax6bc", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 112121212, 1800, 3500, 1.5, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_ax6bc_init, NULL },
{ "[i440BX] Gigabyte GA-686BX", "686bx", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 3.0, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_686bx_init, NULL },
{ "[i440BX] HP Vectra VEi 8", "vei8", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 3.0, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192,1048576, 8192, 255, machine_at_vei8_init, NULL },
{ "[i440BX] Tyan Tsunami ATX", "tsunamiatx", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 112121212, 1800, 3500, 3.5, 5.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_SOUND, 8192,1048576, 8192, 255, machine_at_tsunamiatx_init, at_tsunamiatx_get_device },
{ "[i440BX] SuperMicro Super P6SBA", "p6sba", MACHINE_TYPE_SLOT1, CPU_PKG_SLOT1, 0, 66666667, 100000000, 1800, 3500, 3.0, 8.0, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_p6sba_init, NULL },
#if defined(DEV_BRANCH) && defined(NO_SIO)

321
src/sio/sio_fdc37m60x.c Normal file
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@@ -0,0 +1,321 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the SMSC FDC37M60x Super I/O
*
* Authors: Tiseno100
* Copyright 2020 Tiseno100
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#define SIO_INDEX_PORT dev->sio_index_port
#define INDEX dev->index
/* Current Logical Device Number */
#define CURRENT_LOGICAL_DEVICE dev->regs[0x07]
/* Global Device Configuration */
#define ENABLED dev->device_regs[CURRENT_LOGICAL_DEVICE][0x30]
#define BASE_ADDRESS ((dev->device_regs[CURRENT_LOGICAL_DEVICE][0x60] << 8) | (dev->device_regs[CURRENT_LOGICAL_DEVICE][0x61]))
#define IRQ dev->device_regs[CURRENT_LOGICAL_DEVICE][0x70]
#define DMA dev->device_regs[CURRENT_LOGICAL_DEVICE][0x74]
/* Miscellaneous Chip Functionality */
#define SOFT_RESET (val & 0x01)
#define POWER_CONTROL dev->regs[0x22]
#ifdef ENABLE_FDC37M60X_LOG
int fdc37m60x_do_log = ENABLE_FDC37M60X_LOG;
static void
fdc37m60x_log(const char *fmt, ...)
{
va_list ap;
if (fdc37m60x_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define fdc37m60x_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], device_regs[10][256], cfg_lock, ide_function;
uint16_t sio_index_port;
fdc_t *fdc_controller;
serial_t *uart[2];
} fdc37m60x_t;
void fdc37m60x_fdc_handler(fdc37m60x_t *dev);
void fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev);
void fdc37m60x_lpt_handler(fdc37m60x_t *dev);
void fdc37m60x_logical_device_handler(fdc37m60x_t *dev);
static void fdc37m60x_reset(void *priv);
static void
fdc37m60x_write(uint16_t addr, uint8_t val, void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
switch (addr)
{
case 0x3f0:
case 0x370:
INDEX = val;
/* Enter/Escape Configuration Mode */
if (val == 0x55)
dev->cfg_lock = 0;
else if (val == 0xaa)
dev->cfg_lock = 1;
break;
case 0x3f1:
case 0x371:
if (!dev->cfg_lock)
{
switch (INDEX)
{
/* Global Configuration */
case 0x02:
dev->regs[INDEX] = val;
if (SOFT_RESET)
fdc37m60x_reset(dev);
break;
case 0x07:
CURRENT_LOGICAL_DEVICE = (val & 0x0f);
break;
case 0x22:
POWER_CONTROL = val & 0x3f;
break;
case 0x23:
dev->regs[INDEX] = val & 0x3f;
break;
case 0x24:
dev->regs[INDEX] = val & 0xce;
break;
/* Device Configuration */
case 0x30:
case 0x60:
case 0x61:
case 0x70:
case 0x74:
if(CURRENT_LOGICAL_DEVICE <= 0x81) /* Avoid Overflow */
dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] = (INDEX == 0x30) ? (val & 1) : val;
fdc37m60x_logical_device_handler(dev);
break;
}
}
break;
}
}
static uint8_t
fdc37m60x_read(uint16_t addr, void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
return (INDEX >= 0x30) ? dev->device_regs[CURRENT_LOGICAL_DEVICE][INDEX] : dev->regs[INDEX];
}
void fdc37m60x_fdc_handler(fdc37m60x_t *dev)
{
fdc_remove(dev->fdc_controller);
if(ENABLED || (POWER_CONTROL & 0x01))
{
fdc_set_base(dev->fdc_controller, BASE_ADDRESS);
fdc_set_irq(dev->fdc_controller, IRQ & 0xf);
fdc_set_dma_ch(dev->fdc_controller, DMA & 0x07);
fdc37m60x_log("SMC60x-FDC: BASE %04x IRQ %d DMA %d\n", BASE_ADDRESS, IRQ & 0xf, DMA & 0x07);
}
}
void fdc37m60x_uart_handler(uint8_t num, fdc37m60x_t *dev)
{
serial_remove(dev->uart[num & 1]);
if(!(num & 1) ? (ENABLED || (POWER_CONTROL & 0x10)) : (ENABLED || (POWER_CONTROL & 0x20)))
{
serial_setup(dev->uart[num & 1], BASE_ADDRESS, IRQ & 0xf);
fdc37m60x_log("SMC60x-UART%d: BASE %04x IRQ %d\n", num & 1, BASE_ADDRESS, IRQ & 0xf);
}
}
void fdc37m60x_lpt_handler(fdc37m60x_t *dev)
{
lpt1_remove();
if(ENABLED || (POWER_CONTROL & 0x80))
{
lpt1_init(BASE_ADDRESS);
lpt1_irq(IRQ & 0xf);
fdc37m60x_log("SMC60x-LPT: BASE %04x IRQ %d\n", BASE_ADDRESS, IRQ & 0xf);
}
}
void fdc37m60x_logical_device_handler(fdc37m60x_t *dev)
{
/*
Register 07h:
Device 0: FDC
Device 3: LPT
Device 4: UART1
Device 5: UART2
*/
switch (CURRENT_LOGICAL_DEVICE)
{
case 0x00:
fdc37m60x_fdc_handler(dev);
break;
case 0x03:
fdc37m60x_lpt_handler(dev);
break;
case 0x04:
fdc37m60x_uart_handler(0, dev);
break;
case 0x05:
fdc37m60x_uart_handler(1, dev);
break;
}
}
static void
fdc37m60x_reset(void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
CURRENT_LOGICAL_DEVICE = 0x00;
dev->regs[0x22] = 0x00;
dev->regs[0x26] = SIO_INDEX_PORT & 0xf;
dev->regs[0x27] = (SIO_INDEX_PORT >> 4) & 0xf;
/* FDC Registers */
dev->device_regs[0][0x30] = 0x00;
dev->device_regs[0][0x60] = 0x03; /* Base Address */
dev->device_regs[0][0x61] = 0xf0;
dev->device_regs[0][0x70] = 0x06;
dev->device_regs[0][0x74] = 0x02;
/* LPT Port */
dev->device_regs[3][0x30] = 0x00;
dev->device_regs[3][0x60] = 0x00; /* Base Address */
dev->device_regs[3][0x61] = 0x00;
dev->device_regs[3][0x64] = 0x04;
/* UART1 */
dev->device_regs[4][0x30] = 0x00;
dev->device_regs[4][0x60] = 0x00; /* Base Address */
dev->device_regs[4][0x61] = 0x00;
dev->device_regs[4][0x70] = 0x00;
/* UART2 */
dev->device_regs[5][0x30] = 0x00;
dev->device_regs[5][0x60] = 0x00; /* Base Address */
dev->device_regs[5][0x61] = 0x00;
dev->device_regs[5][0x70] = 0x00;
/* AUX */
dev->device_regs[8][0x30] = 0x00;
fdc37m60x_fdc_handler(dev);
fdc37m60x_uart_handler(0, dev);
fdc37m60x_uart_handler(1, dev);
fdc37m60x_lpt_handler(dev);
}
static void
fdc37m60x_close(void *priv)
{
fdc37m60x_t *dev = (fdc37m60x_t *)priv;
free(dev);
}
static void *
fdc37m60x_init(const device_t *info)
{
fdc37m60x_t *dev = (fdc37m60x_t *)malloc(sizeof(fdc37m60x_t));
memset(dev, 0, sizeof(fdc37m60x_t));
SIO_INDEX_PORT = info->local;
dev->regs[0x20] = 0x47;
dev->regs[0x24] = 0x04;
dev->device_regs[0][0xf0] = 0x0e;
dev->device_regs[0][0xf2] = 0xff;
dev->device_regs[3][0xf0] = 0x3c;
dev->device_regs[4][0xf1] = 0x02;
dev->device_regs[4][0xf2] = 0x03;
dev->device_regs[8][0xc0] = 0x06;
dev->device_regs[8][0xc1] = 0x03;
dev->fdc_controller = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
io_sethandler(SIO_INDEX_PORT, 0x0002, fdc37m60x_read, NULL, NULL, fdc37m60x_write, NULL, NULL, dev);
return dev;
}
const device_t fdc37m60x_device = {
"SMSC FDC37M60X",
0,
0x03f0,
fdc37m60x_init,
fdc37m60x_close,
NULL,
{NULL},
NULL,
NULL,
NULL};
const device_t fdc37m60x_370_device = {
"SMSC FDC37M60X with 10K Pull Up Resistor",
0,
0x0370,
fdc37m60x_init,
fdc37m60x_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

297
src/sio/sio_pc87311.c Normal file
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@@ -0,0 +1,297 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the National Semiconductor PC87311 Super I/O
*
* Authors: Tiseno100
* Copyright 2020 Tiseno100
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#define HAS_IDE_FUNCTIONALITY dev->ide_function
/* Basic Functionalities */
#define FUNCTION_ENABLE dev->regs[0x00]
#define FUNCTION_ADDRESS dev->regs[0x01]
#define POWER_TEST dev->regs[0x02]
/* Base Addresses */
#define LPT_BA (FUNCTION_ADDRESS & 0x03)
#define UART1_BA ((FUNCTION_ADDRESS >> 2) & 0x03)
#define UART2_BA ((FUNCTION_ADDRESS >> 4) & 0x03)
#define COM_BA ((FUNCTION_ADDRESS >> 6) & 0x03)
#ifdef ENABLE_PC87311_LOG
int pc87311_do_log = ENABLE_PC87311_LOG;
static void
pc87311_log(const char *fmt, ...)
{
va_list ap;
if (pc87311_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define pc87311_log(fmt, ...)
#endif
typedef struct
{
uint8_t index, regs[256], cfg_lock, ide_function;
uint16_t base, irq;
fdc_t *fdc_controller;
serial_t *uart[2];
} pc87311_t;
void pc87311_fdc_handler(pc87311_t *dev);
void pc87311_uart_handler(uint8_t num, pc87311_t *dev);
void pc87311_lpt_handler(pc87311_t *dev);
void pc87311_ide_handler(pc87311_t *dev);
void pc87311_enable(pc87311_t *dev);
static void
pc87311_write(uint16_t addr, uint8_t val, void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
switch (addr)
{
case 0x398:
case 0x26e:
dev->index = val;
break;
case 0x399:
case 0x26f:
switch (dev->index)
{
case 0x00:
FUNCTION_ENABLE = val;
break;
case 0x01:
FUNCTION_ADDRESS = val;
break;
case 0x02:
POWER_TEST = val;
break;
}
break;
}
pc87311_enable(dev);
}
static uint8_t
pc87311_read(uint16_t addr, void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
return dev->regs[dev->index];
}
void pc87311_fdc_handler(pc87311_t *dev)
{
fdc_remove(dev->fdc_controller);
fdc_set_base(dev->fdc_controller, (FUNCTION_ENABLE & 0x20) ? 0x0370 : 0x03f0);
pc87311_log("PC87311-FDC: BASE %04x\n", (FUNCTION_ENABLE & 0x20) ? 0x0370 : 0x03f0);
}
uint16_t com3(pc87311_t *dev)
{
switch (COM_BA)
{
case 0:
return 0x03e8;
case 1:
return 0x0338;
case 2:
return 0x02e8;
case 3:
return 0x0220;
default:
return 0x03e8;
}
}
uint16_t com4(pc87311_t *dev)
{
switch (COM_BA)
{
case 0:
return 0x02e8;
case 1:
return 0x0238;
case 2:
return 0x02e0;
case 3:
return 0x0228;
default:
return 0x02e8;
}
}
void pc87311_uart_handler(uint8_t num, pc87311_t *dev)
{
serial_remove(dev->uart[num & 1]);
switch ((!num & 1) ? UART1_BA : UART2_BA)
{
case 0:
dev->base = 0x03f8;
dev->irq = 4;
break;
case 1:
dev->base = 0x02f8;
dev->irq = 3;
break;
case 2:
dev->base = com3(dev);
dev->irq = 4;
break;
case 3:
dev->base = com4(dev);
dev->irq = 3;
break;
}
serial_setup(dev->uart[num & 1], dev->base, dev->irq);
pc87311_log("PC87311-UART%01x: BASE %04x IRQ %01x\n", num & 1, dev->base, dev->irq);
}
void pc87311_lpt_handler(pc87311_t *dev)
{
lpt1_remove();
switch (LPT_BA)
{
case 0:
dev->base = 0x0378;
dev->irq = (POWER_TEST & 0x08) ? 7 : 5;
break;
case 1:
dev->base = 0x03bc;
dev->irq = 7;
break;
case 2:
dev->base = 0x0278;
dev->irq = 5;
break;
}
lpt1_init(dev->base);
lpt1_irq(dev->irq);
pc87311_log("PC87311-LPT: BASE %04x IRQ %01x\n", dev->base, dev->irq);
}
void pc87311_ide_handler(pc87311_t *dev)
{
ide_pri_disable();
ide_sec_disable();
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
ide_pri_enable();
if (FUNCTION_ENABLE & 0x80)
{
ide_set_base(1, 0x170);
ide_set_side(1, 0x376);
ide_sec_enable();
}
pc87311_log("PC87311-IDE: PRI %01x SEC %01x\n", (FUNCTION_ENABLE >> 6) & 1, (FUNCTION_ENABLE >> 7) & 1);
}
void pc87311_enable(pc87311_t *dev)
{
(FUNCTION_ENABLE & 0x01) ? pc87311_lpt_handler(dev) : lpt1_remove();
(FUNCTION_ENABLE & 0x02) ? pc87311_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_ENABLE & 0x04) ? pc87311_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_ENABLE & 0x08) ? pc87311_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (FUNCTION_ENABLE & 0x20)
pc87311_fdc_handler(dev);
if (HAS_IDE_FUNCTIONALITY)
{
(FUNCTION_ENABLE & 0x40) ? pc87311_ide_handler(dev) : ide_pri_disable();
(FUNCTION_ADDRESS & 0x80) ? pc87311_ide_handler(dev) : ide_sec_disable();
}
}
static void
pc87311_close(void *priv)
{
pc87311_t *dev = (pc87311_t *)priv;
free(dev);
}
static void *
pc87311_init(const device_t *info)
{
pc87311_t *dev = (pc87311_t *)malloc(sizeof(pc87311_t));
memset(dev, 0, sizeof(pc87311_t));
/* Avoid conflicting with machines that make no use of the PC87311 Internal IDE */
HAS_IDE_FUNCTIONALITY = info->local;
dev->fdc_controller = device_add(&fdc_at_nsc_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
if (HAS_IDE_FUNCTIONALITY)
device_add(&ide_isa_2ch_device);
io_sethandler(0x0398, 0x0002, pc87311_read, NULL, NULL, pc87311_write, NULL, NULL, dev);
io_sethandler(0x026e, 0x0002, pc87311_read, NULL, NULL, pc87311_write, NULL, NULL, dev);
pc87311_enable(dev);
return dev;
}
const device_t pc87311_device = {
"National Semiconductor PC87311",
0,
0,
pc87311_init,
pc87311_close,
NULL,
{NULL},
NULL,
NULL,
NULL};
const device_t pc87311_ide_device = {
"National Semiconductor PC87311 with IDE functionality",
0,
1,
pc87311_init,
pc87311_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

341
src/sio/sio_prime3c.c Normal file
View File

@@ -0,0 +1,341 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the LG Prime3C Super I/O
*
* Authors: Tiseno100
* Copyright 2020 Tiseno100
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#ifdef ENABLE_PRIME3C_LOG
int prime3c_do_log = ENABLE_PRIME3C_LOG;
static void
prime3c_log(const char *fmt, ...)
{
va_list ap;
if (prime3c_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define prime3c_log(fmt, ...)
#endif
/* Function Select(Note on prime3c_enable) */
#define FUNCTION_SELECT dev->regs[0xc2]
/* Base Address Registers */
#define FDC_BASE_ADDRESS dev->regs[0xc3]
#define IDE_BASE_ADDRESS dev->regs[0xc4]
#define IDE_SIDE_ADDRESS dev->regs[0xc5]
#define LPT_BASE_ADDRESS dev->regs[0xc6]
#define UART1_BASE_ADDRESS dev->regs[0xc7]
#define UART2_BASE_ADDRESS dev->regs[0xc8]
/* FDC/LPT Configuration */
#define FDC_LPT_DMA dev->regs[0xc9]
#define FDC_LPT_IRQ dev->regs[0xca]
/* UART 1/2 Configuration */
#define UART_IRQ dev->regs[0xcb]
/* Miscellaneous Configuration*/
#define FDC_SWAP (dev->regs[0xd6] & 0x01)
/* IDE functionality(Note on Init) */
#define HAS_IDE_FUNCTIONALITY dev->ide_function
typedef struct
{
uint8_t index, regs[256], cfg_lock, ide_function;
fdc_t *fdc_controller;
serial_t *uart[2];
} prime3c_t;
void prime3c_fdc_handler(prime3c_t *dev);
void prime3c_uart_handler(uint8_t num, prime3c_t *dev);
void prime3c_lpt_handler(prime3c_t *dev);
void prime3c_ide_handler(prime3c_t *dev);
void prime3c_enable(prime3c_t *dev);
static void
prime3c_write(uint16_t addr, uint8_t val, void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
switch (addr)
{
case 0x398:
dev->index = val;
/* Enter/Escape Configuration Mode */
if (val == 0x33)
dev->cfg_lock = 0;
else if (val == 0x55)
dev->cfg_lock = 1;
break;
case 0x399:
if (!dev->cfg_lock)
{
switch (dev->index)
{
case 0xc2:
FUNCTION_SELECT = val & 0xbf;
prime3c_enable(dev);
break;
case 0xc3:
FDC_BASE_ADDRESS = val & 0xfc;
prime3c_fdc_handler(dev);
break;
case 0xc4:
IDE_BASE_ADDRESS = val & 0xfc;
if (HAS_IDE_FUNCTIONALITY)
prime3c_ide_handler(dev);
break;
case 0xc5:
IDE_SIDE_ADDRESS = (val & 0xfc) | 0x02;
prime3c_ide_handler(dev);
break;
case 0xc6:
LPT_BASE_ADDRESS = val;
break;
case 0xc7:
UART1_BASE_ADDRESS = val & 0xfe;
prime3c_uart_handler(0, dev);
break;
case 0xc8:
UART2_BASE_ADDRESS = val & 0xfe;
prime3c_uart_handler(1, dev);
break;
case 0xc9:
FDC_LPT_DMA = val;
prime3c_fdc_handler(dev);
break;
case 0xca:
FDC_LPT_IRQ = val;
prime3c_fdc_handler(dev);
prime3c_lpt_handler(dev);
break;
case 0xcb:
UART_IRQ = val;
prime3c_uart_handler(0, dev);
prime3c_uart_handler(1, dev);
break;
case 0xcd:
case 0xce:
dev->regs[dev->index] = val;
break;
case 0xcf:
dev->regs[dev->index] = val & 0x3f;
break;
case 0xd0:
dev->regs[dev->index] = val & 0xfc;
break;
case 0xd1:
dev->regs[dev->index] = val & 0x3f;
break;
case 0xd3:
dev->regs[dev->index] = val & 0x7c;
break;
case 0xd5:
case 0xd6:
case 0xd7:
case 0xd8:
dev->regs[dev->index] = val;
break;
}
}
break;
}
}
static uint8_t
prime3c_read(uint16_t addr, void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
return dev->regs[dev->index];
}
void prime3c_fdc_handler(prime3c_t *dev)
{
fdc_remove(dev->fdc_controller);
if (FUNCTION_SELECT & 0x10)
{
fdc_set_base(dev->fdc_controller, FDC_BASE_ADDRESS << 2);
fdc_set_irq(dev->fdc_controller, (FDC_LPT_IRQ >> 4) & 0xf);
fdc_set_dma_ch(dev->fdc_controller, (FDC_LPT_DMA >> 4) & 0xf);
fdc_set_swap(dev->fdc_controller, FDC_SWAP);
prime3c_log("Prime3C-FDC: BASE %04x IRQ %01x DMA %01x\n", FDC_BASE_ADDRESS << 2, (FDC_LPT_IRQ >> 4) & 0xf, (FDC_LPT_DMA >> 4) & 0xf);
}
}
void prime3c_uart_handler(uint8_t num, prime3c_t *dev)
{
serial_remove(dev->uart[num & 1]);
if (FUNCTION_SELECT & (!(num & 1) ? 0x04 : 0x08))
{
serial_setup(dev->uart[num & 1], (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
prime3c_log("Prime3C-UART%01x: BASE %04x IRQ %01x\n", num & 1, (!(num & 1) ? UART1_BASE_ADDRESS : UART2_BASE_ADDRESS) << 2, (UART_IRQ >> (!(num & 1) ? 4 : 0)) & 0xf);
}
}
void prime3c_lpt_handler(prime3c_t *dev)
{
lpt1_remove();
if (!(FUNCTION_SELECT & 0x03))
{
lpt1_init(LPT_BASE_ADDRESS << 2);
lpt1_irq(FDC_LPT_IRQ & 0xf);
prime3c_log("Prime3C-LPT: BASE %04x IRQ %02x\n", LPT_BASE_ADDRESS << 2, FDC_LPT_IRQ & 0xf);
}
}
void prime3c_ide_handler(prime3c_t *dev)
{
ide_pri_disable();
if (FUNCTION_SELECT & 0x20)
{
ide_set_base(0, IDE_BASE_ADDRESS << 2);
ide_set_side(0, IDE_SIDE_ADDRESS << 2);
ide_pri_enable();
prime3c_log("Prime3C-IDE: BASE %04x SIDE %04x\n", IDE_BASE_ADDRESS << 2, IDE_SIDE_ADDRESS << 2);
}
}
void prime3c_enable(prime3c_t *dev)
{
/*
Simulate a device enable/disable scenario
Register C2: Function Select
Bit 7: Gameport
Bit 6: Reserved
Bit 5: IDE
Bit 4: FDC
Bit 3: UART 2
Bit 2: UART 1
Bit 1/0: PIO (0/0 Unidirectional , 0/1 ECP, 1/0 EPP, 1/1 Disabled)
Note: 86Box LPT is simplistic and can't do ECP or EPP.
*/
!(FUNCTION_SELECT & 0x03) ? prime3c_lpt_handler(dev) : lpt1_remove();
(FUNCTION_SELECT & 0x04) ? prime3c_uart_handler(0, dev) : serial_remove(dev->uart[0]);
(FUNCTION_SELECT & 0x08) ? prime3c_uart_handler(1, dev) : serial_remove(dev->uart[1]);
(FUNCTION_SELECT & 0x10) ? prime3c_fdc_handler(dev) : fdc_remove(dev->fdc_controller);
if (HAS_IDE_FUNCTIONALITY)
(FUNCTION_SELECT & 0x20) ? prime3c_ide_handler(dev) : ide_pri_disable();
}
static void
prime3c_close(void *priv)
{
prime3c_t *dev = (prime3c_t *)priv;
free(dev);
}
static void *
prime3c_init(const device_t *info)
{
prime3c_t *dev = (prime3c_t *)malloc(sizeof(prime3c_t));
memset(dev, 0, sizeof(prime3c_t));
/* Avoid conflicting with machines that make no use of the Prime3C Internal IDE */
HAS_IDE_FUNCTIONALITY = info->local;
dev->regs[0xc0] = 0x3c;
dev->regs[0xc2] = 0x03;
dev->regs[0xc3] = 0x3c;
dev->regs[0xc4] = 0x3c;
dev->regs[0xc5] = 0x3d;
dev->regs[0xd5] = 0x3c;
dev->fdc_controller = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
if (HAS_IDE_FUNCTIONALITY)
device_add(&ide_isa_device);
prime3c_fdc_handler(dev);
prime3c_uart_handler(0, dev);
prime3c_uart_handler(1, dev);
prime3c_lpt_handler(dev);
if (HAS_IDE_FUNCTIONALITY)
prime3c_ide_handler(dev);
io_sethandler(0x0398, 0x0002, prime3c_read, NULL, NULL, prime3c_write, NULL, NULL, dev);
return dev;
}
const device_t prime3c_device = {
"Goldstar Prime3C",
0,
0,
prime3c_init,
prime3c_close,
NULL,
{NULL},
NULL,
NULL,
NULL};
const device_t prime3c_ide_device = {
"Goldstar Prime3C with IDE functionality",
0,
1,
prime3c_init,
prime3c_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

5
src/win/Makefile.mingw
View File

@@ -639,8 +639,9 @@ DEVOBJ := bugger.o hwm.o hwm_lm75.o hwm_lm78.o hwm_gl518sm.o hwm_vt82c686.o ibm
SIOOBJ := sio_acc3221.o \
sio_f82c710.o sio_82091aa.o \
sio_fdc37c661.o sio_fdc37c66x.o sio_fdc37c669.o sio_fdc37c93x.o \
sio_pc87306.o sio_pc87307.o sio_pc87309.o sio_pc87332.o \
sio_fdc37c661.o sio_fdc37c66x.o sio_fdc37c669.o sio_fdc37c93x.o sio_fdc37m60x.o \
sio_pc87306.o sio_pc87307.o sio_pc87309.o sio_pc87311.o sio_pc87332.o \
sio_prime3c.o \
sio_w83787f.o \
sio_w83877f.o sio_w83977f.o \
sio_um8669f.o \