Added initial Apollo Pro emulation
- Added the Apollo Pro Northbridge - Added a PC Partner board (APRO + 586B Southbridge) **COMPATIBLE WITH VIA C3!**
This commit is contained in:
tiseno100
GitHub
@@ -66,6 +66,7 @@ extern const device_t sis_85c50x_device;
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/* VIA */
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extern const device_t via_mvp3_device;
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extern const device_t via_apro_device;
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/* VLSI */
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extern const device_t vlsi_scamp_device;
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345
src/chipset/via_apro.c
Normal file
345
src/chipset/via_apro.c
Normal file
@@ -0,0 +1,345 @@
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/*
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86Box A hypervisor and IBM PC system emulator that specializes in
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running old operating systems and software designed for IBM
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PC systems and compatibles from 1981 through fairly recent
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system designs based on the PCI bus.
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<This file is part of the 86Box distribution.>
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VIA Apollo Pro North Bridge emulation
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VT82C691 used in the PC Partner APAS3 board
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based on the model of VIA MVP3 by mooch & Sarah
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Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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Copyright(C) 2020 Tiseno100
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Copyright(C) 2020 Melissa Goad
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Copyright(C) 2020 Miran Grca
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Note: Due to 99.9% similarities with the VP3, MVP3 but also other later Apollo chipsets. We probably should create a common Apollo tree
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just like the Intel 4x0 series.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include "86box.h"
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#include "mem.h"
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#include "86box_io.h"
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#include "rom.h"
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#include "pci.h"
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#include "device.h"
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#include "keyboard.h"
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#include "chipset.h"
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typedef struct via_apro_t
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{
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uint8_t pci_conf[2][256];
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} via_apro_t;
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static void
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apro_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void
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via_apro_pci_regs(via_apro_t *dev)
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{
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memset(dev, 0, sizeof(via_apro_t));
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// Host Bridge registers
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dev->pci_conf[0][0x00] = 0x06; // VIA
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dev->pci_conf[0][0x01] = 0x11;
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dev->pci_conf[0][0x02] = 0x91; // VT82C691
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dev->pci_conf[0][0x03] = 0x06;
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dev->pci_conf[0][0x04] = 6; // Command
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dev->pci_conf[0][0x05] = 0;
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// These(06h-0fh) probably aren't needed but as they're referenced by the MVP3 chipset code i added them too
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dev->pci_conf[0][0x06] = 0; // Status
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dev->pci_conf[0][0x07] = 0;
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dev->pci_conf[0][0x09] = 0; // Program Interface
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dev->pci_conf[0][0x0a] = 0; // Sub Class Code
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dev->pci_conf[0][0x0b] = 0; // Base Class Code
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dev->pci_conf[0][0x0c] = 0; // reserved
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dev->pci_conf[0][0x0d] = 0; // Latency Timer
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dev->pci_conf[0][0x0e] = 0; // Header Type
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dev->pci_conf[0][0x0f] = 0; // Built-in Self test
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dev->pci_conf[0][0x10] = 0x08; // Graphics Aperature Base
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dev->pci_conf[0][0x34] = 0xa0; // Capability Pointer
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dev->pci_conf[0][0x56] = 1; // Bank 6 Ending
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dev->pci_conf[0][0x57] = 1; // Bank 7 Ending
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dev->pci_conf[0][0x5a] = 1; // Bank 0 Ending
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dev->pci_conf[0][0x5b] = 1; // Bank 1 Ending
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dev->pci_conf[0][0x5c] = 1; // Bank 2 Ending
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dev->pci_conf[0][0x5d] = 1; // Bank 3 Ending
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dev->pci_conf[0][0x5e] = 1; // Bank 4 Ending
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dev->pci_conf[0][0x5f] = 1; // Bank 5 Ending
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dev->pci_conf[0][0x64] = 0xec; // DRAM Timing for Banks 0,1
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dev->pci_conf[0][0x65] = 0xec; // DRAM Timing for Banks 2,3
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dev->pci_conf[0][0x66] = 0xec; // DRAM Timing for Banks 4,5
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dev->pci_conf[0][0x67] = 0x01; // DRAM Timing for Banks 6,7
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dev->pci_conf[0][0x6b] = 1; // DRAM Abritration control
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dev->pci_conf[0][0xa4] = 0x03; // AGP Status
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dev->pci_conf[0][0xa5] = 0x02;
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dev->pci_conf[0][0xa6] = 0;
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dev->pci_conf[0][0xa7] = 0x07;
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// PCI-to-PCI
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dev->pci_conf[1][0x00] = 0x06; // VIA
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dev->pci_conf[1][0x01] = 0x11;
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dev->pci_conf[1][0x02] = 0x91; // VT82C691
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dev->pci_conf[1][0x03] = 0x06;
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dev->pci_conf[1][0x04] = 7; // Command
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dev->pci_conf[1][0x05] = 0;
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dev->pci_conf[1][0x06] = 0x20; // Status
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dev->pci_conf[1][0x07] = 0x02;
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dev->pci_conf[1][0x09] = 0; // Program Interface
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dev->pci_conf[1][0x0A] = 4; // Sub Class Code
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dev->pci_conf[1][0x0B] = 6; // Base Class Code
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dev->pci_conf[1][0x0C] = 0; // reserved
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dev->pci_conf[1][0x0D] = 0; // Latency Timer
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dev->pci_conf[1][0x0E] = 1; // Header Type
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dev->pci_conf[1][0x0F] = 0; // Built-in Self test
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dev->pci_conf[1][0x1c] = 0xf0; // I/O Base
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dev->pci_conf[1][0x20] = 0xf0; // Memory Base
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dev->pci_conf[1][0x21] = 0xff;
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dev->pci_conf[1][0x24] = 0xf0;
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dev->pci_conf[1][0x25] = 0xff;
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}
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static void
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host_bridge_write(int func, int addr, uint8_t val, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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// Read-Only registers. Exact same as MVP3
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if ((addr < 4) || ((addr >= 5) && (addr < 7)) || ((addr >= 8) && (addr < 0xd)) || ((addr >= 0xe) && (addr < 0x12)) ||
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((addr >= 0x14) && (addr < 0x50)) || ((addr >= 0x79) && (addr < 0x7e)) || ((addr >= 0x85) && (addr < 0x88)) ||
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((addr >= 0x8c) && (addr < 0xa8)) || ((addr >= 0xad) && (addr < 0xfd)))
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return;
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switch(addr){
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case 0x04: // Command
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dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
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case 0x07: // Status
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dev->pci_conf[0][0x07] &= ~(val & 0xb0);
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break;
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case 0x12: //Graphics Aperature Base
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dev->pci_conf[0][0x12] = (val & 0xf0);
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break;
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case 0x13:
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dev->pci_conf[0][0x13] = val;
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break;
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case 0x61: // Shadow RAM control 1
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if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
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apro_map(0xc0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
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apro_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
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apro_map(0xc8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
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apro_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x61] = val;
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return;
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case 0x62: // Shadow RAM Control 2
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if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
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apro_map(0xd0000, 0x04000, val & 0x03);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
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apro_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
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apro_map(0xd8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
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apro_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x62] = val;
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return;
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case 0x63: // Shadow RAM Control 3
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if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
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apro_map(0xf0000, 0x10000, (val & 0x30) >> 4);
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shadowbios = (((val & 0x30) >> 4) & 0x02);
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}
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if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
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apro_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
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dev->pci_conf[0][0x63] = val;
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return;
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//In case we throw somewhere
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default:
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dev->pci_conf[0][addr] = val;
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break;
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}
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}
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static void
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pci_to_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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if (func != 1)
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return;
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//As with MVP3. Same deal
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if ((addr < 4) || ((addr >= 5) && (addr < 7)) ||
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((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) ||
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((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) ||
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(addr >= 0x43))
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return;
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switch(addr) {
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case 0x04:
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dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47);
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break;
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case 0x07:
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dev->pci_conf[1][0x07] &= ~(val & 0x30);
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break;
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case 0x20: // Memory Base
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dev->pci_conf[1][0x20] = val & 0xf0;
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break;
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case 0x22: // Memory Limit
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dev->pci_conf[1][0x22] = val & 0xf0;
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break;
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case 0x24: // Prefetchable Memory base
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dev->pci_conf[1][0x24] = val & 0xf0;
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break;
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case 0x26: // Prefetchable Memory limit
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dev->pci_conf[1][0x26] = val & 0xf0;
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break;
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default:
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dev->pci_conf[1][addr] = val;
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break;
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}
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}
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static uint8_t
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via_apro_read(int func, int addr, void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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uint8_t ret = 0xff;
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switch(func) {
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case 0:
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ret = dev->pci_conf[0][addr];
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break;
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case 1:
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ret = dev->pci_conf[1][addr];
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break;
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}
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return ret;
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}
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static void
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via_apro_write(int func, int addr, uint8_t val, void *priv)
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{
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switch(func) {
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case 0:
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host_bridge_write(func, addr, val, priv);
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break;
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case 1:
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pci_to_pci_bridge_write(func, addr, val, priv);
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break;
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}
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}
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static void
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via_apro_reset(void *priv)
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{
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via_apro_write(0, 0x63, via_apro_read(0, 0x63, priv) & 0xcf, priv);
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}
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static void *
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via_apro_init(const device_t *info)
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{
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via_apro_t *dev = (via_apro_t *) malloc(sizeof(via_apro_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, via_apro_read, via_apro_write, dev);
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via_apro_pci_regs(dev);
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return dev;
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}
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static void
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via_apro_close(void *priv)
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{
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via_apro_t *dev = (via_apro_t *) priv;
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free(dev);
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}
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const device_t via_apro_device = {
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"VIA Apollo Pro",
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DEVICE_PCI,
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0,
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via_apro_init,
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via_apro_close,
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via_apro_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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@@ -30,6 +30,7 @@
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#include "hdc_ide.h"
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#include "keyboard.h"
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#include "intel_flash.h"
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#include "via_vt82c586b.h"
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#include "intel_sio.h"
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#include "piix.h"
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#include "sio.h"
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@@ -237,13 +238,13 @@ machine_at_borapro_init(const machine_t *model)
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return ret;
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}
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#if defined(DEV_BRANCH) && defined(USE_I686)
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int
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machine_at_p6bxt_init(const machine_t *model)
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machine_at_apas3_init(const machine_t *model)
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{
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int ret;
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ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN",
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ret = bios_load_linear(L"roms/machines/apas3/V0218SAG.BIN",
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0x000c0000, 262144, 0);
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if (bios_only || !ret)
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@@ -253,23 +254,21 @@ machine_at_p6bxt_init(const machine_t *model)
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pci_init(PCI_CONFIG_TYPE_1);
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pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
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pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
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pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
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pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */
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pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
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pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1);
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pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2);
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pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3);
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pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
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pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
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device_add(&i440bx_device);
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device_add(&piix4e_device);
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device_add(&w83977tf_device);
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device_add(&via_apro_device);
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device_add(&via_vt82c586b_device);
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device_add(&fdc37c669_device);
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device_add(&keyboard_ps2_pci_device);
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device_add(&sst_flash_39sf020_device);
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spd_register(SPD_TYPE_SDRAM, 0x7, 256);
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return ret;
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}
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#endif
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int
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machine_at_63a_init(const machine_t *model)
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@@ -304,4 +303,4 @@ machine_at_63a_init(const machine_t *model)
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spd_register(SPD_TYPE_SDRAM, 0x3, 256);
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return ret;
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}
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||||
}
|
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@@ -300,6 +300,7 @@ extern int machine_at_586t2_init(const machine_t *);
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extern int machine_at_807ds_init(const machine_t *);
|
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|
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extern int machine_at_mvp3_init(const machine_t *);
|
||||
extern int machine_at_apas3_init(const machine_t *);
|
||||
|
||||
#ifdef EMU_DEVICE_H
|
||||
extern const device_t *at_pb640_get_device(void);
|
||||
@@ -316,6 +317,7 @@ extern int machine_at_6abx3_init(const machine_t *);
|
||||
extern int machine_at_p2bls_init(const machine_t *);
|
||||
extern int machine_at_borapro_init(const machine_t *);
|
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extern int machine_at_63a_init(const machine_t *);
|
||||
extern int machine_at_vim863s_init(const machine_t *);
|
||||
|
||||
/* m_at_t3100e.c */
|
||||
extern int machine_at_t3100e_init(const machine_t *);
|
||||
|
||||
@@ -244,14 +244,15 @@ const machine_t machines[] = {
|
||||
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
|
||||
#endif
|
||||
#if defined(DEV_BRANCH) && defined(USE_I686)
|
||||
{ "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL },
|
||||
{ "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron},{"VIA", cpus_Cyrix3},{"", NULL},{"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL },
|
||||
|
||||
{ "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_p6bxt_init, NULL },
|
||||
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
|
||||
{ "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL },
|
||||
#else
|
||||
{ "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL },
|
||||
{ "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_borapro_init, NULL },
|
||||
|
||||
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
|
||||
{ "[Socket 370 APRO] PC Partner APAS3", "apas3", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL },
|
||||
#endif
|
||||
|
||||
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
|
||||
|
||||
@@ -575,7 +575,7 @@ CPUOBJ := cpu.o cpu_table.o \
|
||||
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
|
||||
intel_4x0.o neat.o opti495.o scamp.o scat.o \
|
||||
sis_85c471.o sis_85c496.o \
|
||||
via_mvp3.o wd76c10.o
|
||||
via_mvp3.o via_apro.o wd76c10.o
|
||||
|
||||
MCHOBJ := machine.o machine_table.o \
|
||||
m_xt.o m_xt_compaq.o \
|
||||
|
||||
@@ -580,7 +580,7 @@ CPUOBJ := cpu.o cpu_table.o \
|
||||
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
|
||||
intel_4x0.o neat.o opti495.o scamp.o scat.o \
|
||||
sis_85c471.o sis_85c496.o \
|
||||
via_mvp3.o wd76c10.o
|
||||
via_mvp3.o via_apro.o wd76c10.o
|
||||
|
||||
MCHOBJ := machine.o machine_table.o \
|
||||
m_xt.o m_xt_compaq.o \
|
||||
|
||||
Reference in New Issue
Block a user