Merge pull request #4589 from jriwanek-forks/ni
More named initializers in cpu table
This commit is contained in:
@@ -1009,12 +1009,92 @@ const cpu_family_t cpu_families[] = {
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.name = "i386SX",
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.internal_name = "i386sx",
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.cpus = (const CPU[]) {
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{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386SX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386SX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386SX,
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@@ -1022,12 +1102,92 @@ const cpu_family_t cpu_families[] = {
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.name = "Am386SX",
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.internal_name = "am386sx",
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.cpus = (const CPU[]) {
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{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386SX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386SX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386DX,
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@@ -1035,12 +1195,92 @@ const cpu_family_t cpu_families[] = {
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.name = "i386DX",
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.internal_name = "i386dx",
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.cpus = (const CPU[]) {
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{"16", CPU_386DX, fpus_80386, 16000000, 1, 5000, 0x0308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386DX, fpus_80386, 20000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x0308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x0308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386DX_DESKPRO386,
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@@ -1048,10 +1288,58 @@ const cpu_family_t cpu_families[] = {
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.name = "i386DX",
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.internal_name = "i386dx_deskpro386",
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.cpus = (const CPU[]) {
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{"16", CPU_386DX, fpus_80286, 16000000, 1, 5000, 0x0308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386DX, fpus_80386, 20000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80286,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386DX,
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@@ -1059,10 +1347,58 @@ const cpu_family_t cpu_families[] = {
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.name = "RapidCAD",
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.internal_name = "rapidcad",
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.cpus = (const CPU[]) {
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{"25", CPU_RAPIDCAD, fpus_internal, 25000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3},
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{"33", CPU_RAPIDCAD, fpus_internal, 33333333, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4},
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{"40", CPU_RAPIDCAD, fpus_internal, 40000000, 1, 5000, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "25",
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.cpu_type = CPU_RAPIDCAD,
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.fpus = fpus_internal,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0340,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_RAPIDCAD,
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.fpus = fpus_internal,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0340,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_RAPIDCAD,
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.fpus = fpus_internal,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x0340,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386DX,
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@@ -1070,10 +1406,58 @@ const cpu_family_t cpu_families[] = {
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.name = "Am386DX",
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.internal_name = "am386dx",
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.cpus = (const CPU[]) {
|
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{"25", CPU_386DX, fpus_80386, 25000000, 1, 5000, 0x0308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386DX, fpus_80386, 33333333, 1, 5000, 0x0308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386DX, fpus_80386, 40000000, 1, 5000, 0x0308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "25",
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.cpu_type = CPU_386DX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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||||
.voltage = 5000,
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||||
.edx_reset = 0x0308,
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.cpuid_model = 0,
|
||||
.cyrix_id = 0,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 4,
|
||||
.mem_write_cycles = 4,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 3
|
||||
},
|
||||
{
|
||||
.name = "33",
|
||||
.cpu_type = CPU_386DX,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 33333333,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x0308,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 6,
|
||||
.mem_write_cycles = 6,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 4
|
||||
},
|
||||
{
|
||||
.name = "40",
|
||||
.cpu_type = CPU_386DX,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 40000000,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x0308,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 7,
|
||||
.mem_write_cycles = 7,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 5
|
||||
},
|
||||
{ .name = "", 0 }
|
||||
}
|
||||
}, {
|
||||
.package = CPU_PKG_M6117,
|
||||
@@ -1081,9 +1465,41 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "M6117",
|
||||
.internal_name = "m6117",
|
||||
.cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */
|
||||
{"33", CPU_386SX, fpus_none, 33333333, 1, 5000, 0x2309, 0, 0, 0, 6,6,3,3, 4},
|
||||
{"40", CPU_386SX, fpus_none, 40000000, 1, 5000, 0x2309, 0, 0, 0, 7,7,3,3, 5},
|
||||
{"", 0}
|
||||
{
|
||||
.name = "33",
|
||||
.cpu_type = CPU_386SX,
|
||||
.fpus = fpus_none,
|
||||
.rspeed = 33333333,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x2309,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 6,
|
||||
.mem_write_cycles = 6,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 4
|
||||
},
|
||||
{
|
||||
.name = "40",
|
||||
.cpu_type = CPU_386SX,
|
||||
.fpus = fpus_none,
|
||||
.rspeed = 40000000,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x2309,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 7,
|
||||
.mem_write_cycles = 7,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 5
|
||||
},
|
||||
{ .name = "", 0 }
|
||||
}
|
||||
}, {
|
||||
.package = CPU_PKG_386SLC_IBM,
|
||||
@@ -1175,10 +1591,58 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "Cx486DLC",
|
||||
.internal_name = "cx486dlc",
|
||||
.cpus = (const CPU[]) {
|
||||
{"25", CPU_486DLC, fpus_80386, 25000000, 1, 5000, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3},
|
||||
{"33", CPU_486DLC, fpus_80386, 33333333, 1, 5000, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4},
|
||||
{"40", CPU_486DLC, fpus_80386, 40000000, 1, 5000, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5},
|
||||
{"", 0}
|
||||
{
|
||||
.name = "25",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 25000000,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x401,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0001,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 4,
|
||||
.mem_write_cycles = 4,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 3
|
||||
},
|
||||
{
|
||||
.name = "33",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 33333333,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x401,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0001,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 6,
|
||||
.mem_write_cycles = 6,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 4
|
||||
},
|
||||
{
|
||||
.name = "40",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 40000000,
|
||||
.multi = 1,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x401,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0001,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 7,
|
||||
.mem_write_cycles = 7,
|
||||
.cache_read_cycles = 3,
|
||||
.cache_write_cycles = 3,
|
||||
.atclk_div = 5
|
||||
},
|
||||
{ .name = "", 0 }
|
||||
}
|
||||
}, {
|
||||
.package = CPU_PKG_386DX,
|
||||
@@ -1186,11 +1650,75 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "Cx486DRx2",
|
||||
.internal_name = "cx486drx2",
|
||||
.cpus = (const CPU[]) {
|
||||
{"32", CPU_486DLC, fpus_80386, 32000000, 2, 5000, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4},
|
||||
{"40", CPU_486DLC, fpus_80386, 40000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
|
||||
{"50", CPU_486DLC, fpus_80386, 50000000, 2, 5000, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6},
|
||||
{"66", CPU_486DLC, fpus_80386, 66666666, 2, 5000, 0x407, 0, 0x0007, 0, 12,12,6,6, 8},
|
||||
{"", 0}
|
||||
{
|
||||
.name = "32",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 32000000,
|
||||
.multi = 2,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x407,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0007,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 6,
|
||||
.mem_write_cycles = 6,
|
||||
.cache_read_cycles = 6,
|
||||
.cache_write_cycles = 6,
|
||||
.atclk_div = 4
|
||||
},
|
||||
{
|
||||
.name = "40",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 40000000,
|
||||
.multi = 2,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x407,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0007,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 8,
|
||||
.mem_write_cycles = 8,
|
||||
.cache_read_cycles = 6,
|
||||
.cache_write_cycles = 6,
|
||||
.atclk_div = 6
|
||||
},
|
||||
{
|
||||
.name = "50",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 50000000,
|
||||
.multi = 2,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x407,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0007,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 8,
|
||||
.mem_write_cycles = 8,
|
||||
.cache_read_cycles = 6,
|
||||
.cache_write_cycles = 6,
|
||||
.atclk_div = 6
|
||||
},
|
||||
{
|
||||
.name = "66",
|
||||
.cpu_type = CPU_486DLC,
|
||||
.fpus = fpus_80386,
|
||||
.rspeed = 66666666,
|
||||
.multi = 2,
|
||||
.voltage = 5000,
|
||||
.edx_reset = 0x407,
|
||||
.cpuid_model = 0,
|
||||
.cyrix_id = 0x0007,
|
||||
.cpu_flags = 0,
|
||||
.mem_read_cycles = 12,
|
||||
.mem_write_cycles = 12,
|
||||
.cache_read_cycles = 6,
|
||||
.cache_write_cycles = 6,
|
||||
.atclk_div = 8
|
||||
},
|
||||
{ .name = "", 0 }
|
||||
}
|
||||
}, {
|
||||
.package = CPU_PKG_SOCKET1,
|
||||
|
Reference in New Issue
Block a user