80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

More fixes to the BT485 RAM DAC code;

Browse Source 
Small changes to the CL-GD 54xx ext. palette handling.
This commit is contained in:
OBattler
2018-10-03 05:42:10 +02:00
parent 988cbe4414
commit 6b938d63c3
3 changed files with 66 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

78
src/video/vid_bt485_ramdac.c
View File

@@ -9,7 +9,7 @@
* Emulation of the Brooktree BT485 and BT485A true colour * Emulation of the Brooktree BT485 and BT485A true colour
* RAM DAC's. * RAM DAC's.
* *
* Version: @(#)vid_bt485_ramdac.c 1.0.8 2018/10/03 * Version: @(#)vid_bt485_ramdac.c 1.0.9 2018/10/03
* *
* Authors: Miran Grca, <mgrca8@gmail.com> * Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, * TheCollector1995,
@@ -59,16 +59,21 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
{ {
uint32_t o32; uint32_t o32;
uint8_t *cd; uint8_t *cd;
uint8_t index;
uint8_t rs = (addr & 0x03); uint8_t rs = (addr & 0x03);
rs |= (!!rs2 << 2); rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3); rs |= (!!rs3 << 3);
switch (rs) { switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */ case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
svga_out(addr, val, svga);
if ((ramdac->type >= BT485) && (svga->hwcursor.xsize == 64))
svga->dac_write |= ((int) (ramdac->cr3 & 0x03) << 8);
break;
case 0x01: /* Palette Data Register (RS value = 0001) */ case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */ case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
case 0x03: /* Palette Read Index Register (RS value = 0011) */ case 0x03: /* Palette Read Index Register (RS value = 0011) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */ case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
svga_out(addr, val, svga); svga_out(addr, val, svga);
break; break;
@@ -85,21 +90,22 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
svga->dac_pos++; svga->dac_pos++;
break; break;
case 2: case 2:
ramdac->extpal[svga->dac_write & 3].r = svga->dac_r; index = svga->dac_write & 3;
ramdac->extpal[svga->dac_write & 3].g = svga->dac_g; ramdac->extpal[index].r = svga->dac_r;
ramdac->extpal[svga->dac_write & 3].b = val; ramdac->extpal[index].g = svga->dac_g;
ramdac->extpal[index].b = val;
if (svga->ramdac_type == RAMDAC_8BIT) if (svga->ramdac_type == RAMDAC_8BIT)
ramdac->extpallook[svga->dac_write & 3] = makecol32(ramdac->extpal[svga->dac_write].r & 0x3f, ramdac->extpal[svga->dac_write].g & 0x3f, ramdac->extpal[svga->dac_write].b & 0x3f); ramdac->extpallook[index] = makecol32(ramdac->extpal[index].r, ramdac->extpal[index].g, ramdac->extpal[index].b);
else else
ramdac->extpallook[svga->dac_write & 3] = makecol32(video_6to8[ramdac->extpal[svga->dac_write].r & 0x3f], video_6to8[ramdac->extpal[svga->dac_write].g & 0x3f], video_6to8[ramdac->extpal[svga->dac_write].b & 0x3f]); ramdac->extpallook[index] = makecol32(video_6to8[ramdac->extpal[index].r & 0x3f], video_6to8[ramdac->extpal[index].g & 0x3f], video_6to8[ramdac->extpal[index].b & 0x3f]);
if ((svga->crtc[0x33] & 0x40) && ((svga->dac_write & 3) == 0)) { if ((svga->crtc[0x33] & 0x40) && !index) {
o32 = svga->overscan_color; o32 = svga->overscan_color;
svga->overscan_color = ramdac->extpallook[0]; svga->overscan_color = ramdac->extpallook[0];
if (o32 != svga->overscan_color) if (o32 != svga->overscan_color)
svga_recalctimings(svga); svga_recalctimings(svga);
} }
svga->dac_write = (svga->dac_write + 1) & 15; svga->dac_write = (svga->dac_write + 1);
svga->dac_pos = 0; svga->dac_pos = 0;
break; break;
} }
@@ -119,7 +125,7 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
break; break;
case 0x0a: case 0x0a:
if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) { if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) {
switch (svga->dac_pos) { switch ((svga->dac_write & 0xff)) {
case 0x01: case 0x01:
/* Command Register 3 (RS value = 1010) */ /* Command Register 3 (RS value = 1010) */
ramdac->cr3 = val; ramdac->cr3 = val;
@@ -128,7 +134,7 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize; svga->hwcursor.x = ramdac->hwc_x - svga->hwcursor.xsize;
svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize; svga->hwcursor.y = ramdac->hwc_y - svga->hwcursor.ysize;
if (svga->hwcursor.xsize == 64) if (svga->hwcursor.xsize == 64)
svga->dac_pos = (svga->dac_pos & 0x00ff) | ((val & 0x03) << 8); svga->dac_write = (svga->dac_write & 0x00ff) | ((val & 0x03) << 8);
svga_recalctimings(svga); svga_recalctimings(svga);
break; break;
case 0x02: case 0x02:
@@ -137,8 +143,8 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
case 0x22: case 0x22:
if (ramdac->type != BT485A) if (ramdac->type != BT485A)
break; break;
else if (svga->dac_pos == 2) { else if (svga->dac_write == 2) {
ramdac->cr4 = val;; ramdac->cr4 = val;
break; break;
} }
break; break;
@@ -150,12 +156,11 @@ bt485_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, bt485_ramdac_t *r
cd = (uint8_t *) ramdac->cursor64_data; cd = (uint8_t *) ramdac->cursor64_data;
else else
cd = (uint8_t *) ramdac->cursor32_data; cd = (uint8_t *) ramdac->cursor32_data;
cd[svga->dac_pos] = val;
svga->dac_pos++; cd[svga->dac_write] = val;
if (svga->hwcursor.xsize == 32)
svga->dac_pos &= 0x00ff; svga->dac_write++;
else svga->dac_write &= ((svga->hwcursor.xsize == 64) ? 0x03ff : 0x00ff);
svga->dac_pos &= 0x03ff;
break; break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */ case 0x0c: /* Cursor X Low Register (RS value = 1100) */
ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val; ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
@@ -184,6 +189,7 @@ bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t
{ {
uint8_t temp = 0xff; uint8_t temp = 0xff;
uint8_t *cd; uint8_t *cd;
uint8_t index;
uint8_t rs = (addr & 0x03); uint8_t rs = (addr & 0x03);
rs |= (!!rs2 << 2); rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3); rs |= (!!rs3 << 3);
@@ -198,18 +204,28 @@ bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t
temp = svga_in(addr, svga); temp = svga_in(addr, svga);
break; break;
case 0x05: /* Ext Palette Data Register (RS value = 0101) */ case 0x05: /* Ext Palette Data Register (RS value = 0101) */
svga->dac_status = 0; index = svga->dac_read & 3;
svga->dac_status = 3;
switch (svga->dac_pos) { switch (svga->dac_pos) {
case 0: case 0:
svga->dac_pos++; svga->dac_pos++;
temp = ramdac->extpal[svga->dac_read].r & 0x3f; if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].r;
else
temp = ramdac->extpal[index].r & 0x3f;
case 1: case 1:
svga->dac_pos++; svga->dac_pos++;
temp = ramdac->extpal[svga->dac_read].g & 0x3f; if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].g;
else
temp = ramdac->extpal[index].g & 0x3f;
case 2: case 2:
svga->dac_pos=0; svga->dac_pos=0;
svga->dac_read = (svga->dac_read + 1) & 15; svga->dac_read = svga->dac_read + 1;
temp = ramdac->extpal[(svga->dac_read - 1) & 15].b & 0x3f; if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].b;
else
temp = ramdac->extpal[index].b & 0x3f;
} }
break; break;
case 0x06: /* Command Register 0 (RS value = 0110) */ case 0x06: /* Command Register 0 (RS value = 0110) */
@@ -223,7 +239,7 @@ bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t
break; break;
case 0x0a: case 0x0a:
if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) { if ((ramdac->type >= BT485) && (ramdac->cr0 & 0x80)) {
switch (svga->dac_pos) { switch ((svga->dac_write & 0xff)) {
case 0x00: case 0x00:
temp = ramdac->status; temp = ramdac->status;
break; break;
@@ -236,7 +252,7 @@ bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t
case 0x22: case 0x22:
if (ramdac->type != BT485A) if (ramdac->type != BT485A)
break; break;
else if (svga->dac_pos == 2) { else if (svga->dac_write == 2) {
temp = ramdac->cr4; temp = ramdac->cr4;
break; break;
} else { } else {
@@ -255,10 +271,10 @@ bt485_ramdac_in(uint16_t addr, int rs2, int rs3, bt485_ramdac_t *ramdac, svga_t
else else
cd = (uint8_t *) ramdac->cursor32_data; cd = (uint8_t *) ramdac->cursor32_data;
temp = cd[svga->dac_pos]; temp = cd[svga->dac_write];
svga->dac_pos++;
svga->dac_pos &= ((svga->hwcursor.xsize == 64) ? 0x03ff : 0x00ff); svga->dac_write++;
svga->dac_write &= ((svga->hwcursor.xsize == 64) ? 0x03ff : 0x00ff);
break; break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */ case 0x0c: /* Cursor X Low Register (RS value = 1100) */
temp = ramdac->hwc_x & 0xff; temp = ramdac->hwc_x & 0xff;
@@ -295,13 +311,13 @@ void bt485_init(bt485_ramdac_t *ramdac, svga_t *svga, uint8_t type)
But all other sources seem to assume SR7=1 and SR6=0. */ But all other sources seem to assume SR7=1 and SR6=0. */
switch (ramdac->type) { switch (ramdac->type) {
case BT484: case BT484:
ramdac->status = 0x80; ramdac->status = 0x40;
break; break;
case ATT20C504: case ATT20C504:
ramdac->status = 0x40; ramdac->status = 0x40;
break; break;
case BT485: case BT485:
ramdac->status = 0xa0; ramdac->status = 0x60;
break; break;
case ATT20C505: case ATT20C505:
ramdac->status = 0xd0; ramdac->status = 0xd0;

2
src/video/vid_bt485_ramdac.h
View File

@@ -9,7 +9,7 @@
* Header of the emulation of the Brooktree BT485 and BT485A * Header of the emulation of the Brooktree BT485 and BT485A
* true colour RAM DAC's. * true colour RAM DAC's.
* *
* Version: @(#)vid_bt485_ramdac.h 1.0.1 2018/10/03 * Version: @(#)vid_bt485_ramdac.h 1.0.2 2018/10/03
* *
* Authors: Miran Grca, <mgrca8@gmail.com> * Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, * TheCollector1995,

36
src/video/vid_cl54xx.c
View File

@@ -9,7 +9,7 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428, * Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported). * CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
* *
* Version: @(#)vid_cl_54xx.c 1.0.22 2018/09/30 * Version: @(#)vid_cl_54xx.c 1.0.23 2018/10/03
* *
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/> * Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Barry Rodewald, * Barry Rodewald,
@@ -227,7 +227,7 @@ gd54xx_out(uint16_t addr, uint8_t val, void *p)
svga_t *svga = &gd54xx->svga; svga_t *svga = &gd54xx->svga;
uint8_t old; uint8_t old;
int c; int c;
uint8_t o; uint8_t o, index;
uint32_t o32; uint32_t o32;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1)) if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
@@ -352,17 +352,18 @@ gd54xx_out(uint16_t addr, uint8_t val, void *p)
break; break;
case 2: case 2:
if (svga->seqregs[0x12] & 2) { if (svga->seqregs[0x12] & 2) {
gd54xx->extpal[svga->dac_write].r = svga->dac_r; index = svga->dac_write & 0x0f;
gd54xx->extpal[svga->dac_write].g = svga->dac_g; gd54xx->extpal[index].r = svga->dac_r;
gd54xx->extpal[svga->dac_write].b = val; gd54xx->extpal[index].g = svga->dac_g;
gd54xx->extpallook[svga->dac_write & 15] = makecol32(video_6to8[gd54xx->extpal[svga->dac_write].r & 0x3f], video_6to8[gd54xx->extpal[svga->dac_write].g & 0x3f], video_6to8[gd54xx->extpal[svga->dac_write].b & 0x3f]); gd54xx->extpal[index].b = val;
gd54xx->extpallook[index] = makecol32(video_6to8[gd54xx->extpal[index].r & 0x3f], video_6to8[gd54xx->extpal[index].g & 0x3f], video_6to8[gd54xx->extpal[index].b & 0x3f]);
if ((svga->seqregs[0x12] & 0x80) && ((svga->dac_write & 15) == 2)) { if ((svga->seqregs[0x12] & 0x80) && ((svga->dac_write & 15) == 2)) {
o32 = svga->overscan_color; o32 = svga->overscan_color;
svga->overscan_color = gd54xx->extpallook[2]; svga->overscan_color = gd54xx->extpallook[2];
if (o32 != svga->overscan_color) if (o32 != svga->overscan_color)
svga_recalctimings(svga); svga_recalctimings(svga);
} }
svga->dac_write = (svga->dac_write + 1) & 15; svga->dac_write = (svga->dac_write + 1);
} else { } else {
svga->vgapal[svga->dac_write].r = svga->dac_r; svga->vgapal[svga->dac_write].r = svga->dac_r;
svga->vgapal[svga->dac_write].g = svga->dac_g; svga->vgapal[svga->dac_write].g = svga->dac_g;
@@ -543,7 +544,7 @@ gd54xx_in(uint16_t addr, void *p)
gd54xx_t *gd54xx = (gd54xx_t *)p; gd54xx_t *gd54xx = (gd54xx_t *)p;
svga_t *svga = &gd54xx->svga; svga_t *svga = &gd54xx->svga;
uint8_t temp; uint8_t index, temp;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3d0) && !(svga->miscout & 1)) if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3d0) && !(svga->miscout & 1))
addr ^= 0x60; addr ^= 0x60;
@@ -595,28 +596,27 @@ gd54xx_in(uint16_t addr, void *p)
break; break;
case 0x3c9: case 0x3c9:
svga->dac_status = 3; svga->dac_status = 3;
index = svga->dac_read & 0x0f;
switch (svga->dac_pos) { switch (svga->dac_pos) {
case 0: case 0:
svga->dac_pos++; svga->dac_pos++;
if (svga->seqregs[0x12] & 2) if (svga->seqregs[0x12] & 2)
return gd54xx->extpal[svga->dac_read].r & 0x3f; return gd54xx->extpal[index].r & 0x3f;
else else
return svga->vgapal[svga->dac_read].r & 0x3f; return svga->vgapal[index].r & 0x3f;
case 1: case 1:
svga->dac_pos++; svga->dac_pos++;
if (svga->seqregs[0x12] & 2) if (svga->seqregs[0x12] & 2)
return gd54xx->extpal[svga->dac_read].g & 0x3f; return gd54xx->extpal[index].g & 0x3f;
else else
return svga->vgapal[svga->dac_read].g & 0x3f; return svga->vgapal[index].g & 0x3f;
case 2: case 2:
svga->dac_pos=0; svga->dac_pos=0;
if (svga->seqregs[0x12] & 2) { svga->dac_read = (svga->dac_read + 1) & 255;
svga->dac_read = (svga->dac_read + 1) & 15; if (svga->seqregs[0x12] & 2)
return gd54xx->extpal[(svga->dac_read - 1) & 15].b & 0x3f; return gd54xx->extpal[index].b & 0x3f;
} else { else
svga->dac_read = (svga->dac_read + 1) & 255;
return svga->vgapal[(svga->dac_read - 1) & 255].b & 0x3f; return svga->vgapal[(svga->dac_read - 1) & 255].b & 0x3f;
}
} }
return 0xFF; return 0xFF;
case 0x3C6: case 0x3C6: