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Fixed PIC ELCR priv pointers for the STPC and VIA VT82C49x.

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This commit is contained in:
OBattler
2020-10-18 15:34:52 +02:00
parent 3234e65e06
commit 6c72d834ef
2 changed files with 6 additions and 6 deletions
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4
src/chipset/stpc.c
View File

@@ -689,7 +689,7 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x56: case 0x57:
pic_elcr_write(dev->reg_offset, val, NULL);
pic_elcr_write(dev->reg_offset, val, (dev->reg_offset & 1) ? &pic2 : &pic);
if (dev->reg_offset == 0x57)
refresh_at_enable = (val & 0x01);
break;
@@ -717,7 +717,7 @@ stpc_reg_read(uint16_t addr, void *priv)
return 0xff; /* Cyrix CPU registers: let the CPU code handle these */
else if ((dev->reg_offset == 0x56) || (dev->reg_offset == 0x57)) {
/* ELCR is in here, not in port 4D0h. */
ret = pic_elcr_read(dev->reg_offset, NULL);
ret = pic_elcr_read(dev->reg_offset, (dev->reg_offset & 1) ? &pic2 : &pic);
if (dev->reg_offset == 0x57)
ret |= (dev->regs[dev->reg_offset] & 0x01);
} else

8
src/chipset/via_vt82c49x.c
View File

@@ -222,9 +222,9 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
/* Edge/Level IRQ Control */
case 0x62: case 0x63:
if (dev->index == 0x63)
pic_elcr_write(dev->index, val & 0xde, NULL);
pic_elcr_write(dev->index, val & 0xde, &pic2);
else {
pic_elcr_write(dev->index, val & 0xf8, NULL);
pic_elcr_write(dev->index, val & 0xf8, &pic);
pic_elcr_set_enabled(val & 0x01);
}
break;
@@ -254,9 +254,9 @@ vt82c49x_read(uint16_t addr, void *priv)
switch (addr) {
case 0xa9:
if (dev->index == 0x63)
ret = pic_elcr_read(dev->index, NULL) | (dev->regs[dev->index] & 0x01);
ret = pic_elcr_read(dev->index, &pic2) | (dev->regs[dev->index] & 0x01);
else if (dev->index == 0x62)
ret = pic_elcr_read(dev->index, NULL) | (dev->regs[dev->index] & 0x07);
ret = pic_elcr_read(dev->index, &pic) | (dev->regs[dev->index] & 0x07);
else
ret = dev->regs[dev->index];
break;