Add the AMD Am486DXL and DXL2.

Has otherwise Intel-compatible SMM with an SMBase at 60000h.

src/cpu/cpu.c

@@ -110,7 +110,7 @@ int		isa_cycles,
 
  		is286, is386, is486 = 1,
 		cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
-		is_am486, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
+		is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
 
 		timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
 		timing_mm, timing_mml, timing_bt, timing_bnt,
@@ -369,14 +369,15 @@ cpu_set(void)
 		   (cpu_s->cpu_type == CPU_IBM486BL);
     is486        = (cpu_s->cpu_type >= CPU_RAPIDCAD);
     is_am486     = (cpu_s->cpu_type == CPU_ENH_Am486DX);
+    is_am486dxl  = (cpu_s->cpu_type == CPU_Am486DXL);
 
     cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel");
     cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix");
 
     /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
-       and the WinChip datasheet claims those are Pentium-compatible as well. */
+       and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/
     is_pentium   = (cpu_isintel && (cpu_s->cpu_type >= CPU_i486SX_SLENH) && (cpu_s->cpu_type < CPU_PENTIUMPRO)) ||
-		   !strcmp(cpu_f->manufacturer, "IDT");
+		   !strcmp(cpu_f->manufacturer, "IDT") || (cpu_s->cpu_type == CPU_Am486DXL);
     is_k5        = !strcmp(cpu_f->manufacturer, "AMD") && (cpu_s->cpu_type > CPU_ENH_Am486DX);
     is_k6        = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
     /* The Samuel 2 datasheet claims it's Celeron-compatible. */

src/cpu/cpu.h

@@ -52,6 +52,7 @@ enum {
     CPU_Cx486S,
     CPU_i486DX,
     CPU_Am486DX,
+    CPU_Am486DXL,
     CPU_Cx486DX,
     CPU_i486SX_SLENH,
     CPU_i486DX_SLENH,

src/cpu/cpu_table.c

@@ -454,7 +454,29 @@ const cpu_family_t cpu_families[] = {
 		{"80",  CPU_Am486DX, fpus_internal, 80000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
 		{"", 0}
 	}
+    }, 
+ {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "AMD",
+	.name = "Am486DXL",
+	.internal_name = "am486dxl",
+	.cpus = (const CPU[]) {
+		{"33",   CPU_Am486DXL,  fpus_internal, 33333333, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  6, 6, 3, 3, 4},
+		{"40",   CPU_Am486DXL,  fpus_internal, 40000000, 1, 5000, 0x422,     0, 0, CPU_SUPPORTS_DYNAREC,  7, 7, 3, 3, 5},
+		{"", 0}
+	}
     }, {
+	.package = CPU_PKG_SOCKET1,
+	.manufacturer = "AMD",
+	.name = "Am486DXL2",
+	.internal_name = "am486dxl2",
+	.cpus = (const CPU[]) {
+		{"50",  CPU_Am486DXL, fpus_internal, 50000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC,  8, 8, 6, 6, 6},
+		{"66",  CPU_Am486DXL, fpus_internal, 66666666, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
+		{"80",  CPU_Am486DXL, fpus_internal, 80000000, 2, 5000, 0x432,     0, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
+		{"", 0}
+	}
+    },     {
 	.package = CPU_PKG_SOCKET3,
 	.manufacturer = "AMD",
 	.name = "Am486DX4",

src/cpu/x86.c

@@ -281,7 +281,7 @@ reset_common(int hard)
     smi_block = 0;
 
     if (hard) {
-	smbase = 0x00030000;
+	smbase = isam486dxl ? 0x00060000 : 0x00030000;
 	ppi_reset();
     }
     in_sys = 0;

src/device/keyboard_at.c

@@ -1061,7 +1061,7 @@ write_output(atkbd_t *dev, uint8_t val)
 		/* Pin 0 selected. */
 		softresetx86(); /*Pulse reset!*/
 		cpu_set_edx();
-		smbase = 0x00030000;
+		smbase = isam486dxl ? 0x00060000 : 0x00030000;
 	}
     }
     /* Mask off the A20 stuff because we use mem_a20_key directly for that. */

src/machine/machine.c

@@ -81,7 +81,7 @@ machine_init_ex(int m)
 
 	/* Reset the memory state. */
 	mem_reset();
-	smbase = 0x00030000;
+	smbase = isam486dxl ? 0x00060000 : 0x00030000;
 
 	lpt_init();
     }