Implementing ESFM timer interface using 86Box's timers; dropping ESFMu's internal timer emulation
Co-authored-by: OBattler <oubattler@gmail.com>
This commit is contained in:
@@ -38,11 +38,6 @@
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#define RSM_FRAC 10
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enum {
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FLAG_CYCLES = 0x02,
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FLAG_OPL3 = 0x01
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};
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typedef struct {
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esfm_chip opl;
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int8_t flags;
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@@ -54,12 +49,53 @@ typedef struct {
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uint16_t timer_count[2];
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uint16_t timer_cur_count[2];
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pc_timer_t timers[2];
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int16_t samples[2];
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int pos;
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int32_t buffer[MUSICBUFLEN * 2];
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} esfm_drv_t;
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enum {
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FLAG_CYCLES = 0x02,
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FLAG_OPL3 = 0x01
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};
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enum {
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STAT_TMR_OVER = 0x60,
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STAT_TMR1_OVER = 0x40,
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STAT_TMR2_OVER = 0x20,
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STAT_TMR_ANY = 0x80
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};
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enum {
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CTRL_RESET = 0x80,
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CTRL_TMR_MASK = 0x60,
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CTRL_TMR1_MASK = 0x40,
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CTRL_TMR2_MASK = 0x20,
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CTRL_TMR2_START = 0x02,
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CTRL_TMR1_START = 0x01
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};
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#ifdef ENABLE_OPL_LOG
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int esfm_do_log = ENABLE_OPL_LOG;
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static void
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esfm_log(const char *fmt, ...)
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{
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va_list ap;
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if (esfm_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define esfm_log(fmt, ...)
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#endif
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void
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esfm_generate_raw(esfm_drv_t *dev, int32_t *bufp)
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{
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@@ -78,6 +114,60 @@ esfm_drv_generate_stream(esfm_drv_t *dev, int32_t *sndptr, uint32_t num)
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}
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}
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static void
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esfm_timer_tick(esfm_drv_t *dev, int tmr)
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{
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dev->timer_cur_count[tmr] = (dev->timer_cur_count[tmr] + 1) & 0xff;
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esfm_log("Ticking timer %i, count now %02X...\n", tmr, dev->timer_cur_count[tmr]);
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if (dev->timer_cur_count[tmr] == 0x00) {
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dev->status |= ((STAT_TMR1_OVER >> tmr) & ~dev->timer_ctrl);
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dev->timer_cur_count[tmr] = dev->timer_count[tmr];
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esfm_log("Count wrapped around to zero, reloading timer %i (%02X), status = %02X...\n", tmr, (STAT_TMR1_OVER >> tmr), dev->status);
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}
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timer_on_auto(&dev->timers[tmr], (tmr == 1) ? 320.0 : 80.0);
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}
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static void
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esfm_timer_control(esfm_drv_t *dev, int tmr, int start)
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{
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timer_on_auto(&dev->timers[tmr], 0.0);
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if (start) {
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esfm_log("Loading timer %i count: %02X = %02X\n", tmr, dev->timer_cur_count[tmr], dev->timer_count[tmr]);
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dev->timer_cur_count[tmr] = dev->timer_count[tmr];
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if (dev->flags & FLAG_OPL3)
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esfm_timer_tick(dev, tmr); /* Per the YMF 262 datasheet, OPL3 starts counting immediately, unlike OPL2. */
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else
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timer_on_auto(&dev->timers[tmr], (tmr == 1) ? 320.0 : 80.0);
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} else {
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esfm_log("Timer %i stopped\n", tmr);
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if (tmr == 1) {
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dev->status &= ~STAT_TMR2_OVER;
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} else
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dev->status &= ~STAT_TMR1_OVER;
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}
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}
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static void
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esfm_timer_1(void *priv)
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{
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esfm_drv_t *dev = (esfm_drv_t *) priv;
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esfm_timer_tick(dev, 0);
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}
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static void
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esfm_timer_2(void *priv)
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{
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esfm_drv_t *dev = (esfm_drv_t *) priv;
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esfm_timer_tick(dev, 1);
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}
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static void
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esfm_drv_set_do_cycles(void *priv, int8_t do_cycles)
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{
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@@ -98,6 +188,9 @@ esfm_drv_init(const device_t *info)
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/* Initialize the ESFMu object. */
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ESFM_init(&dev->opl);
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timer_add(&dev->timers[0], esfm_timer_1, dev, 0);
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timer_add(&dev->timers[1], esfm_timer_2, dev, 0);
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return dev;
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}
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@@ -149,32 +242,131 @@ esfm_drv_read(uint16_t port, void *priv)
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uint8_t ret = 0xff;
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ret = ESFM_read_port(&dev->opl, port & 3);
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switch (port & 0x0003)
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{
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case 0x0000:
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ret = dev->status;
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if (dev->status & STAT_TMR_OVER)
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ret |= STAT_TMR_ANY;
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break;
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case 0x0001:
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ret = ESFM_read_port(&dev->opl, port & 3);
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switch (dev->opl.addr_latch & 0x5ff)
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{
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case 0x402:
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ret = dev->timer_count[0];
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break;
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case 0x403:
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ret = dev->timer_count[1];
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break;
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case 0x404:
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ret = dev->timer_ctrl;
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break;
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}
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break;
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case 0x0002:
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case 0x0003:
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ret = 0xff;
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break;
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}
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pclog("esfm: [%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, port, ret);
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return ret;
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}
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static void
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esfm_drv_write_buffered(esfm_drv_t *dev, uint8_t val)
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{
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ESFM_write_reg_buffered_fast(&dev->opl, dev->opl.addr_latch, val);
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if (dev->opl.native_mode)
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{
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switch (dev->port & 0x5ff)
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{
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case 0x402: /* Timer 1 */
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dev->timer_count[0] = val;
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esfm_log("Timer 0 count now: %i\n", dev->timer_count[0]);
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break;
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case 0x403: /* Timer 2 */
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dev->timer_count[1] = val;
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esfm_log("Timer 1 count now: %i\n", dev->timer_count[1]);
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break;
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case 0x404: /* Timer control */
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if (val & CTRL_RESET) {
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esfm_log("Resetting timer status...\n");
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dev->status &= ~STAT_TMR_OVER;
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} else {
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dev->timer_ctrl = val;
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esfm_timer_control(dev, 0, val & CTRL_TMR1_START);
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esfm_timer_control(dev, 1, val & CTRL_TMR2_START);
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esfm_log("Status mask now %02X (val = %02X)\n", (val & ~CTRL_TMR_MASK) & CTRL_TMR_MASK, val);
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}
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break;
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default:
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break;
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}
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}
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else
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{
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switch (dev->port & 0x1ff)
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{
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case 0x002: /* Timer 1 */
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dev->timer_count[0] = val;
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esfm_log("Timer 0 count now: %i\n", dev->timer_count[0]);
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break;
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case 0x003: /* Timer 2 */
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dev->timer_count[1] = val;
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esfm_log("Timer 1 count now: %i\n", dev->timer_count[1]);
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break;
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case 0x004: /* Timer control */
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if (val & CTRL_RESET) {
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esfm_log("Resetting timer status...\n");
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dev->status &= ~STAT_TMR_OVER;
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} else {
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dev->timer_ctrl = val;
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esfm_timer_control(dev, 0, val & CTRL_TMR1_START);
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esfm_timer_control(dev, 1, val & CTRL_TMR2_START);
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esfm_log("Status mask now %02X (val = %02X)\n", (val & ~CTRL_TMR_MASK) & CTRL_TMR_MASK, val);
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}
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break;
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default:
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break;
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}
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}
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}
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static void
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esfm_drv_write(uint16_t port, uint8_t val, void *priv)
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{
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esfm_drv_t *dev = (esfm_drv_t *) priv;
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pclog("esfm: [%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, port, val);
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if (dev->flags & FLAG_CYCLES)
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cycles -= ((int) (isa_timing * 8));
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esfm_drv_update(dev);
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if (dev->opl.native_mode) {
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if ((port & 3) == 1) {
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ESFM_write_reg_buffered_fast(&dev->opl, dev->opl.addr_latch, val);
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} else {
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if ((port & 0x0003) == 0x0001)
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esfm_drv_write_buffered(dev, val);
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else {
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ESFM_write_port(&dev->opl, port & 3, val);
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dev->port = dev->opl.addr_latch & 0x07ff;
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}
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} else {
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if ((port & 3) == 1 || (port & 3) == 3) {
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ESFM_write_reg_buffered_fast(&dev->opl, dev->opl.addr_latch, val);
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} else {
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if ((port & 0x0001) == 0x0001)
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esfm_drv_write_buffered(dev, val);
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else {
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ESFM_write_port(&dev->opl, port & 3, val);
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dev->port = dev->opl.addr_latch & 0x01ff;
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}
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}
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}
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