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Merge pull request #1263 from tiseno100/master

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Sanitize some old chipset code (Part 2)
This commit is contained in:
Miran Grča
2021-02-03 21:51:32 +01:00
committed by GitHub
parent d8de24ed2f ccb52c4585
commit 955b64367b
2 changed files with 156 additions and 166 deletions
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139
src/chipset/ali1429.c
View File

@@ -29,11 +29,13 @@
#include <86box/timer.h> #include <86box/timer.h>
#include <86box/io.h> #include <86box/io.h>
#include <86box/device.h> #include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/apm.h>
#include <86box/mem.h> #include <86box/mem.h>
#include <86box/fdd.h> #include <86box/fdd.h>
#include <86box/fdc.h> #include <86box/fdc.h>
#include <86box/port_92.h> #include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h> #include <86box/chipset.h>
#define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY) #define disabled_shadow (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
@@ -45,122 +47,108 @@ ali1429_log(const char *fmt, ...)
{ {
va_list ap; va_list ap;
if (ali1429_do_log) { if (ali1429_do_log)
va_start(ap, fmt); {
pclog_ex(fmt, ap); va_start(ap, fmt);
va_end(ap); pclog_ex(fmt, ap);
va_end(ap);
} }
} }
#else #else
#define ali1429_log(fmt, ...) #define ali1429_log(fmt, ...)
#endif #endif
typedef struct typedef struct
{ {
uint8_t index, cfg_locked, uint8_t index, cfg_locked,
regs[256]; regs[256];
smram_t *smram;
} ali1429_t; } ali1429_t;
static void ali1429_shadow_recalc(ali1429_t *dev) static void ali1429_shadow_recalc(ali1429_t *dev)
{ {
uint32_t base, i, can_write, can_read; uint32_t base, i, can_write, can_read;
shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01); shadowbios = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x01);
shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02); shadowbios_write = (dev->regs[0x13] & 0x40) && (dev->regs[0x14] & 0x02);
can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; can_write = (dev->regs[0x14] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; can_read = (dev->regs[0x14] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
for(i = 0; i < 8; i++) for (i = 0; i < 8; i++)
{ {
base = 0xc0000 + (i << 15); base = 0xc0000 + (i << 15);
if(dev->regs[0x13] & (1 << i)) if (dev->regs[0x13] & (1 << i))
mem_set_mem_state_both(base, 0x8000, can_read | can_write); mem_set_mem_state_both(base, 0x8000, can_read | can_write);
else else
mem_set_mem_state_both(base, 0x8000, disabled_shadow); mem_set_mem_state_both(base, 0x8000, disabled_shadow);
}
} flushmmucache();
flushmmucache();
} }
static void static void
ali1429_write(uint16_t addr, uint8_t val, void *priv) ali1429_write(uint16_t addr, uint8_t val, void *priv)
{ {
ali1429_t *dev = (ali1429_t *) priv; ali1429_t *dev = (ali1429_t *)priv;
switch (addr) { switch (addr)
case 0x22: {
dev->index = val; case 0x22:
break; dev->index = val;
break;
case 0x23:
/* Don't log register unlock patterns */ case 0x23:
if(dev->index != 0x03) if (dev->index != 0x03)
ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val); ali1429_log("M1429: dev->regs[%02x] = %02x\n", dev->index, val);
/* Unlock/Lock Registers */ if (dev->index == 0x03)
if(dev->index == 0x03) dev->cfg_locked = !(val == 0xc5);
dev->cfg_locked = !(val == 0xc5);
if(!dev->cfg_locked) if (!dev->cfg_locked)
{ {
dev->regs[dev->index] = val; dev->regs[dev->index] = val;
switch(dev->index){ switch (dev->index)
/* Shadow RAM */ {
case 0x13: case 0x13:
case 0x14: case 0x14:
ali1429_shadow_recalc(dev); ali1429_shadow_recalc(dev);
break; break;
/* Cache */
case 0x18: case 0x18:
cpu_cache_ext_enabled = (val & 0x80); cpu_cache_ext_enabled = !!(val & 2);
break; cpu_update_waitstates();
} break;
}
} }
break; break;
} }
} }
static uint8_t static uint8_t
ali1429_read(uint16_t addr, void *priv) ali1429_read(uint16_t addr, void *priv)
{ {
uint8_t ret = 0xff; ali1429_t *dev = (ali1429_t *)priv;
ali1429_t *dev = (ali1429_t *) priv; return (addr == 0x23) ? dev->regs[dev->index] : 0xff;
switch (addr) {
case 0x23:
/* Do not conflict with Cyrix configuration registers */
if(!(((dev->index >= 0xc0) || (dev->index == 0x20)) && cpu_iscyrix))
ret = dev->regs[dev->index];
break;
}
return ret;
} }
static void static void
ali1429_close(void *priv) ali1429_close(void *priv)
{ {
ali1429_t *dev = (ali1429_t *) priv; ali1429_t *dev = (ali1429_t *)priv;
free(dev); free(dev);
} }
static void * static void *
ali1429_init(const device_t *info) ali1429_init(const device_t *info)
{ {
ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t)); ali1429_t *dev = (ali1429_t *)malloc(sizeof(ali1429_t));
memset(dev, 0, sizeof(ali1429_t)); memset(dev, 0, sizeof(ali1429_t));
/* /*
@@ -168,26 +156,25 @@ ali1429_init(const device_t *info)
22h Index Port 22h Index Port
23h Data Port 23h Data Port
*/ */
io_sethandler(0x022, 0x0001, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev); io_sethandler(0x0022, 0x0002, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev);
io_sethandler(0x023, 0x0001, ali1429_read, NULL, NULL, ali1429_write, NULL, NULL, dev);
dev->cfg_locked = 1; dev->cfg_locked = 1;
device_add(&apm_device);
device_add(&port_92_device); device_add(&port_92_device);
/* dev->smram = smram_add(); */
dev->regs[0x13] = 0x00;
dev->regs[0x14] = 0x00;
ali1429_shadow_recalc(dev);
return dev; return dev;
} }
const device_t ali1429_device = { const device_t ali1429_device = {
"ALi M1429", "ALi M1429",
0, 0,
0, 0,
ali1429_init, ali1429_close, NULL, ali1429_init,
{ NULL }, NULL, NULL, ali1429_close,
NULL NULL,
}; {NULL},
NULL,
NULL,
NULL};

183
src/chipset/opti291.c
View File

@@ -8,9 +8,10 @@
* *
* Implementation of the OPTi 82C291 chipset. * Implementation of the OPTi 82C291 chipset.
* Authors: plant/nerd73 * Authors: plant/nerd73, Tiseno100
* *
* Copyright 2020 plant/nerd73. * Copyright 2020 plant/nerd73.
* Copyright 2021 Tiseno100.
*/ */
#include <stdarg.h> #include <stdarg.h>
#include <stdint.h> #include <stdint.h>
@@ -24,133 +25,135 @@
#include <86box/timer.h> #include <86box/timer.h>
#include <86box/io.h> #include <86box/io.h>
#include <86box/device.h> #include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h> #include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h> #include <86box/port_92.h>
#include <86box/chipset.h> #include <86box/chipset.h>
#ifdef ENABLE_OPTI291_LOG
int opti291_do_log = ENABLE_OPTI291_LOG;
static void
opti291_log(const char *fmt, ...)
{
va_list ap;
if (opti291_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define opti291_log(fmt, ...)
#endif
typedef struct typedef struct
{ {
uint8_t index, uint8_t index, regs[256];
regs[256]; port_92_t *port_92;
port_92_t *port_92;
} opti291_t; } opti291_t;
static void opti291_recalc(opti291_t *dev) static void opti291_recalc(opti291_t *dev)
{ {
uint32_t base; mem_set_mem_state_both(0xf0000, 0x10000, (!(dev->regs[0x23] & 0x40) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
uint32_t i, shflags, write, writef = 0;
for (uint32_t i = 0; i < 4; i++)
{
writef = (dev->regs[0x27] & 0x80) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, ((dev->regs[0x26] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : ((dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
if (!(dev->regs[0x23] & 0x40)) mem_set_mem_state_both(0xd0000 + (i << 14), 0x4000, ((dev->regs[0x25] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : ((dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | writef); mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, ((dev->regs[0x24] & (1 << (i + 4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : ((dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)));
else
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | writef);
for (i = 0; i < 4; i++) {
base = 0xe0000 + (i << 14);
shflags = (dev->regs[0x24] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
write = (dev->regs[0x24] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shflags |= (dev->regs[0x27] & 0x40) ? MEM_WRITE_DISABLED : write;
mem_set_mem_state(base, 0x4000, shflags);
} }
for (i = 0; i < 4; i++) { flushmmucache();
base = 0xd0000 + (i << 14); }
shflags = (dev->regs[0x25] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
write = (dev->regs[0x25] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shflags |= (dev->regs[0x27] & 0x20) ? MEM_WRITE_DISABLED : write;
mem_set_mem_state(base, 0x4000, shflags);
}
for (i = 0; i < 4; i++) {
base = 0xc0000 + (i << 14);
shflags = (dev->regs[0x26] & (1 << (i+4))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
write = (dev->regs[0x26] & (1 << i)) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shflags |= (dev->regs[0x27] & 0x10) ? MEM_WRITE_DISABLED : write;
mem_set_mem_state(base, 0x4000, shflags);
}
flushmmucache();
}
static void static void
opti291_write(uint16_t addr, uint8_t val, void *priv) opti291_write(uint16_t addr, uint8_t val, void *priv)
{ {
opti291_t *dev = (opti291_t *) priv; opti291_t *dev = (opti291_t *)priv;
switch (addr) { switch (addr)
{
case 0x22: case 0x22:
dev->index = val; dev->index = val;
break; break;
case 0x24: case 0x24:
pclog("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val); opti291_log("OPTi 291: dev->regs[%02x] = %02x\n", dev->index, val);
dev->regs[dev->index] = val; switch (dev->index)
{
switch(dev->index){ case 0x20:
case 0x21: dev->regs[dev->index] = val & 0x3f;
cpu_update_waitstates(); break;
break; case 0x21:
case 0x23: dev->regs[dev->index] = val & 0xf3;
case 0x24: break;
case 0x25: case 0x22:
case 0x26: dev->regs[dev->index] = val;
case 0x27: break;
opti291_recalc(dev); case 0x23:
break; case 0x24:
} case 0x25:
case 0x26:
dev->regs[dev->index] = val;
opti291_recalc(dev);
break;
case 0x27:
case 0x28:
dev->regs[dev->index] = val;
break;
case 0x29:
dev->regs[dev->index] = val & 0x0f;
break;
case 0x2a:
case 0x2b:
case 0x2c:
dev->regs[dev->index] = val;
break;
}
break; break;
} }
} }
static uint8_t static uint8_t
opti291_read(uint16_t addr, void *priv) opti291_read(uint16_t addr, void *priv)
{ {
uint8_t ret = 0xff; opti291_t *dev = (opti291_t *)priv;
opti291_t *dev = (opti291_t *) priv;
switch (addr) { return (addr == 0x24) ? dev->regs[dev->index] : 0xff;
case 0x24:
// pclog("OPTi 291: read from dev->regs[%02x]\n", dev->index);
ret = dev->regs[dev->index];
break;
}
return ret;
} }
static void static void
opti291_close(void *priv) opti291_close(void *priv)
{ {
opti291_t *dev = (opti291_t *) priv; opti291_t *dev = (opti291_t *)priv;
free(dev); free(dev);
} }
static void * static void *
opti291_init(const device_t *info) opti291_init(const device_t *info)
{ {
opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t)); opti291_t *dev = (opti291_t *)malloc(sizeof(opti291_t));
memset(dev, 0, sizeof(opti291_t)); memset(dev, 0, sizeof(opti291_t));
io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev); io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
dev->regs[0x23] = 0x40; dev->regs[0x22] = 0xf0;
dev->port_92 = device_add(&port_92_device); dev->regs[0x23] = 0x40;
opti291_recalc(dev); dev->regs[0x28] = 0x08;
dev->regs[0x29] = 0xa0;
return dev; device_add(&port_92_device);
opti291_recalc(dev);
return dev;
} }
const device_t opti291_device = { const device_t opti291_device = {
"OPTi 82C291", "OPTi 82C291",
0, 0,
0, 0,
opti291_init, opti291_close, NULL, opti291_init,
{ NULL }, NULL, NULL, opti291_close,
NULL NULL,
}; {NULL},
NULL,
NULL,
NULL};