Reindented and fixed a bug in chipset/umc_8886.c.
This commit is contained in:
OBattler
@@ -11,48 +11,46 @@
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* Note: This chipset has no datasheet, everything were done via
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* reverse engineering the BIOS of various machines using it.
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*
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*
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* Authors: Tiseno100,
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*
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* Copyright 2021 Tiseno100.
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*/
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/*
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UMC 8886 Configuration Registers
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/* UMC 8886 Configuration Registers
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TODO:
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- More Appropriate Bitmasking(If it's even possible)
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TODO:
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- More Appropriate Bitmasking(If it's even possible)
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Warning: Register documentation may be inaccurate!
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Warning: Register documentation may be inaccurate!
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UMC 8886xx:
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(F: Has No Internal IDE / AF or BF: Has Internal IDE)
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UMC 8886xx:
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(F: Has No Internal IDE / AF or BF: Has Internal IDE)
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Function 0 Register 43:
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Bits 7-4 PCI IRQ for INTB
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Bits 3-0 PCI IRQ for INTA
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Function 0 Register 43:
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Bits 7-4 PCI IRQ for INTB
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Bits 3-0 PCI IRQ for INTA
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Function 0 Register 44:
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Bits 7-4 PCI IRQ for INTD
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Bits 3-0 PCI IRQ for INTC
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Function 0 Register 44:
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Bits 7-4 PCI IRQ for INTD
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Bits 3-0 PCI IRQ for INTC
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Function 0 Register 46:
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Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
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Function 0 Register 46:
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Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
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Function 0 Register 51:
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Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
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Function 0 Register 51:
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Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
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Function 0 Register 56:
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Bit 1-0 ISA Bus Speed
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0 0 PCICLK/3
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0 1 PCICLK/4
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1 0 PCICLK/2
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Function 0 Register 56:
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Bit 1-0 ISA Bus Speed
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0 0 PCICLK/3
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0 1 PCICLK/4
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1 0 PCICLK/2
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Function 0 Register A4:
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Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
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Function 0 Register A4:
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Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
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Function 1 Register 4:
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Bit 0: Enable Internal IDE
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Function 1 Register 4:
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Bit 0: Enable Internal IDE
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*/
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#include <stdarg.h>
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@@ -75,6 +73,7 @@ Bit 0: Enable Internal IDE
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#include <86box/chipset.h>
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#ifdef ENABLE_UMC_8886_LOG
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int umc_8886_do_log = ENABLE_UMC_8886_LOG;
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static void
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@@ -93,6 +92,7 @@ umc_8886_log(const char *fmt, ...)
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#define umc_8886_log(fmt, ...)
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#endif
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/* PCI IRQ Flags */
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#define INTA (PCI_INTA + (2 * !(addr & 1)))
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#define INTB (PCI_INTB + (2 * !(addr & 1)))
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@@ -105,6 +105,7 @@ umc_8886_log(const char *fmt, ...)
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/* Southbridge Revision */
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#define SB_ID dev->sb_id
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typedef struct umc_8886_t
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{
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uint8_t pci_conf_sb[2][256]; /* PCI Registers */
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@@ -112,101 +113,99 @@ typedef struct umc_8886_t
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int has_ide; /* Check if Southbridge Revision is AF or F */
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} umc_8886_t;
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void umc_8886_ide_handler(int status)
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static void
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umc_8886_ide_handler(int status)
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{
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ide_pri_disable();
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ide_sec_disable();
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if (status)
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{
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if (status) {
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ide_pri_enable();
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ide_sec_enable();
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}
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}
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static void
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um8886_write(int func, int addr, uint8_t val, void *priv)
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{
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umc_8886_t *dev = (umc_8886_t *)priv;
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umc_8886_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func);
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if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
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/* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
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if (addr > 3) switch (func) {
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case 0: /* Southbridge */
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switch (addr) {
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case 0x43:
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case 0x44:
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dev->pci_conf_sb[func][addr] = val;
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pci_set_irq_routing(INTA, IRQRECALCA);
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pci_set_irq_routing(INTB, IRQRECALCB);
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break;
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switch (func)
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{
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case 0: /* Southbridge */
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switch (addr)
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{
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case 0x43:
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case 0x44:
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dev->pci_conf_sb[func][addr] = val;
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pci_set_irq_routing(INTA, IRQRECALCA);
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pci_set_irq_routing(INTB, IRQRECALCB);
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break;
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case 0x46:
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dev->pci_conf_sb[func][addr] = val & 0xaf;
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break;
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case 0x46:
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dev->pci_conf_sb[func][addr] = val & 0xaf;
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break;
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case 0x47:
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dev->pci_conf_sb[func][addr] = val & 0x4f;
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break;
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case 0x47:
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dev->pci_conf_sb[func][addr] = val & 0x4f;
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break;
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case 0x56:
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dev->pci_conf_sb[func][addr] = val;
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switch (val & 2) {
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case 0:
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cpu_set_isa_pci_div(3);
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break;
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case 1:
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cpu_set_isa_pci_div(4);
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break;
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case 2:
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cpu_set_isa_pci_div(2);
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break;
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}
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break;
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case 0x56:
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dev->pci_conf_sb[func][addr] = val;
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switch (val & 2)
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{
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case 0:
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cpu_set_isa_pci_div(3);
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break;
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case 1:
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cpu_set_isa_pci_div(4);
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break;
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case 2:
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cpu_set_isa_pci_div(2);
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break;
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}
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break;
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case 0x57:
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dev->pci_conf_sb[func][addr] = val & 0x38;
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break;
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case 0x57:
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dev->pci_conf_sb[func][addr] = val & 0x38;
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break;
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case 0x71:
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dev->pci_conf_sb[func][addr] = val & 1;
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break;
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case 0x71:
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dev->pci_conf_sb[func][addr] = val & 1;
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break;
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case 0x90:
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dev->pci_conf_sb[func][addr] = val & 2;
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break;
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case 0x90:
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dev->pci_conf_sb[func][addr] = val & 2;
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break;
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case 0x92:
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dev->pci_conf_sb[func][addr] = val & 0x1f;
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break;
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case 0x92:
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dev->pci_conf_sb[func][addr] = val & 0x1f;
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break;
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case 0xa0:
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dev->pci_conf_sb[func][addr] = val & 0xfc;
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break;
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case 0xa0:
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dev->pci_conf_sb[func][addr] = val & 0xfc;
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break;
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case 0xa4:
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dev->pci_conf_sb[func][addr] = val & 0x89;
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cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2));
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break;
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case 0xa4:
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dev->pci_conf_sb[func][addr] = val & 0x89;
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cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2));
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break;
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default:
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dev->pci_conf_sb[func][addr] = val;
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break;
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}
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break;
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case 1: /* IDE Controller */
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dev->pci_conf_sb[func][addr] = val;
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if ((addr == 4) && HAS_IDE)
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umc_8886_ide_handler(val & 1);
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break;
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}
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default:
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dev->pci_conf_sb[func][addr] = val;
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break;
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}
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break;
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case 1: /* IDE Controller */
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dev->pci_conf_sb[func][addr] = val;
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if ((addr == 4) && HAS_IDE)
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umc_8886_ide_handler(val & 1);
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break;
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}
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}
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static uint8_t
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um8886_read(int func, int addr, void *priv)
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{
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@@ -214,6 +213,7 @@ um8886_read(int func, int addr, void *priv)
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return dev->pci_conf_sb[func][addr];
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}
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static void
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umc_8886_reset(void *priv)
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{
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@@ -233,16 +233,15 @@ umc_8886_reset(void *priv)
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dev->pci_conf_sb[0][0x0b] = 0x06;
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for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
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pci_set_irq_routing(i, PCI_IRQ_DISABLED);
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pci_set_irq_routing(i, PCI_IRQ_DISABLED);
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if (HAS_IDE)
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{
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dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
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umc_8886_ide_handler(1);
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if (HAS_IDE) {
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dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
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umc_8886_ide_handler(1);
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}
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}
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static void
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umc_8886_close(void *priv)
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{
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@@ -257,7 +256,7 @@ umc_8886_init(const device_t *info)
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umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t));
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memset(dev, 0, sizeof(umc_8886_t));
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dev->has_ide = (info->local && 0x886a);
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dev->has_ide = (info->local == 0x886a);
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pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */
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/* Add IDE if UM8886AF variant */
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