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Reindented and fixed a bug in chipset/umc_8886.c.

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This commit is contained in:
OBattler
2021-04-29 19:57:01 +02:00
parent 37dc30029f
commit 9802dfabff
1 changed files with 101 additions and 102 deletions
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203
src/chipset/umc_8886.c
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@@ -11,48 +11,46 @@
* Note: This chipset has no datasheet, everything were done via * Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it. * reverse engineering the BIOS of various machines using it.
* *
*
* Authors: Tiseno100, * Authors: Tiseno100,
* *
* Copyright 2021 Tiseno100. * Copyright 2021 Tiseno100.
*/ */
/* /* UMC 8886 Configuration Registers
UMC 8886 Configuration Registers
TODO: TODO:
- More Appropriate Bitmasking(If it's even possible) - More Appropriate Bitmasking(If it's even possible)
Warning: Register documentation may be inaccurate! Warning: Register documentation may be inaccurate!
UMC 8886xx: UMC 8886xx:
(F: Has No Internal IDE / AF or BF: Has Internal IDE) (F: Has No Internal IDE / AF or BF: Has Internal IDE)
Function 0 Register 43: Function 0 Register 43:
Bits 7-4 PCI IRQ for INTB Bits 7-4 PCI IRQ for INTB
Bits 3-0 PCI IRQ for INTA Bits 3-0 PCI IRQ for INTA
Function 0 Register 44: Function 0 Register 44:
Bits 7-4 PCI IRQ for INTD Bits 7-4 PCI IRQ for INTD
Bits 3-0 PCI IRQ for INTC Bits 3-0 PCI IRQ for INTC
Function 0 Register 46: Function 0 Register 46:
Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10) Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
Function 0 Register 51: Function 0 Register 51:
Bit 2: VGA Power Down (0: Standard/1: VESA DPMS) Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
Function 0 Register 56: Function 0 Register 56:
Bit 1-0 ISA Bus Speed Bit 1-0 ISA Bus Speed
0 0 PCICLK/3 0 0 PCICLK/3
0 1 PCICLK/4 0 1 PCICLK/4
1 0 PCICLK/2 1 0 PCICLK/2
Function 0 Register A4: Function 0 Register A4:
Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half) Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
Function 1 Register 4: Function 1 Register 4:
Bit 0: Enable Internal IDE Bit 0: Enable Internal IDE
*/ */
#include <stdarg.h> #include <stdarg.h>
@@ -75,6 +73,7 @@ Bit 0: Enable Internal IDE
#include <86box/chipset.h> #include <86box/chipset.h>
#ifdef ENABLE_UMC_8886_LOG #ifdef ENABLE_UMC_8886_LOG
int umc_8886_do_log = ENABLE_UMC_8886_LOG; int umc_8886_do_log = ENABLE_UMC_8886_LOG;
static void static void
@@ -93,6 +92,7 @@ umc_8886_log(const char *fmt, ...)
#define umc_8886_log(fmt, ...) #define umc_8886_log(fmt, ...)
#endif #endif
/* PCI IRQ Flags */ /* PCI IRQ Flags */
#define INTA (PCI_INTA + (2 * !(addr & 1))) #define INTA (PCI_INTA + (2 * !(addr & 1)))
#define INTB (PCI_INTB + (2 * !(addr & 1))) #define INTB (PCI_INTB + (2 * !(addr & 1)))
@@ -105,6 +105,7 @@ umc_8886_log(const char *fmt, ...)
/* Southbridge Revision */ /* Southbridge Revision */
#define SB_ID dev->sb_id #define SB_ID dev->sb_id
typedef struct umc_8886_t typedef struct umc_8886_t
{ {
uint8_t pci_conf_sb[2][256]; /* PCI Registers */ uint8_t pci_conf_sb[2][256]; /* PCI Registers */
@@ -112,101 +113,99 @@ typedef struct umc_8886_t
int has_ide; /* Check if Southbridge Revision is AF or F */ int has_ide; /* Check if Southbridge Revision is AF or F */
} umc_8886_t; } umc_8886_t;
void umc_8886_ide_handler(int status)
static void
umc_8886_ide_handler(int status)
{ {
ide_pri_disable(); ide_pri_disable();
ide_sec_disable(); ide_sec_disable();
if (status) if (status) {
{
ide_pri_enable(); ide_pri_enable();
ide_sec_enable(); ide_sec_enable();
} }
} }
static void static void
um8886_write(int func, int addr, uint8_t val, void *priv) um8886_write(int func, int addr, uint8_t val, void *priv)
{ {
umc_8886_t *dev = (umc_8886_t *)priv; umc_8886_t *dev = (umc_8886_t *)priv;
umc_8886_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func); umc_8886_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func);
if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/ /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
if (addr > 3) switch (func) {
case 0: /* Southbridge */
switch (addr) {
case 0x43:
case 0x44:
dev->pci_conf_sb[func][addr] = val;
pci_set_irq_routing(INTA, IRQRECALCA);
pci_set_irq_routing(INTB, IRQRECALCB);
break;
switch (func) case 0x46:
{ dev->pci_conf_sb[func][addr] = val & 0xaf;
case 0: /* Southbridge */ break;
switch (addr)
{
case 0x43:
case 0x44:
dev->pci_conf_sb[func][addr] = val;
pci_set_irq_routing(INTA, IRQRECALCA);
pci_set_irq_routing(INTB, IRQRECALCB);
break;
case 0x46: case 0x47:
dev->pci_conf_sb[func][addr] = val & 0xaf; dev->pci_conf_sb[func][addr] = val & 0x4f;
break; break;
case 0x47: case 0x56:
dev->pci_conf_sb[func][addr] = val & 0x4f; dev->pci_conf_sb[func][addr] = val;
break; switch (val & 2) {
case 0:
cpu_set_isa_pci_div(3);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(2);
break;
}
break;
case 0x56: case 0x57:
dev->pci_conf_sb[func][addr] = val; dev->pci_conf_sb[func][addr] = val & 0x38;
switch (val & 2) break;
{
case 0:
cpu_set_isa_pci_div(3);
break;
case 1:
cpu_set_isa_pci_div(4);
break;
case 2:
cpu_set_isa_pci_div(2);
break;
}
break;
case 0x57: case 0x71:
dev->pci_conf_sb[func][addr] = val & 0x38; dev->pci_conf_sb[func][addr] = val & 1;
break; break;
case 0x71: case 0x90:
dev->pci_conf_sb[func][addr] = val & 1; dev->pci_conf_sb[func][addr] = val & 2;
break; break;
case 0x90: case 0x92:
dev->pci_conf_sb[func][addr] = val & 2; dev->pci_conf_sb[func][addr] = val & 0x1f;
break; break;
case 0x92: case 0xa0:
dev->pci_conf_sb[func][addr] = val & 0x1f; dev->pci_conf_sb[func][addr] = val & 0xfc;
break; break;
case 0xa0: case 0xa4:
dev->pci_conf_sb[func][addr] = val & 0xfc; dev->pci_conf_sb[func][addr] = val & 0x89;
break; cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2));
break;
case 0xa4: default:
dev->pci_conf_sb[func][addr] = val & 0x89; dev->pci_conf_sb[func][addr] = val;
cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2)); break;
break; }
break;
default: case 1: /* IDE Controller */
dev->pci_conf_sb[func][addr] = val; dev->pci_conf_sb[func][addr] = val;
break; if ((addr == 4) && HAS_IDE)
} umc_8886_ide_handler(val & 1);
break; break;
case 1: /* IDE Controller */ }
dev->pci_conf_sb[func][addr] = val;
if ((addr == 4) && HAS_IDE)
umc_8886_ide_handler(val & 1);
break;
}
} }
static uint8_t static uint8_t
um8886_read(int func, int addr, void *priv) um8886_read(int func, int addr, void *priv)
{ {
@@ -214,6 +213,7 @@ um8886_read(int func, int addr, void *priv)
return dev->pci_conf_sb[func][addr]; return dev->pci_conf_sb[func][addr];
} }
static void static void
umc_8886_reset(void *priv) umc_8886_reset(void *priv)
{ {
@@ -233,16 +233,15 @@ umc_8886_reset(void *priv)
dev->pci_conf_sb[0][0x0b] = 0x06; dev->pci_conf_sb[0][0x0b] = 0x06;
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */ for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED); pci_set_irq_routing(i, PCI_IRQ_DISABLED);
if (HAS_IDE) if (HAS_IDE) {
{ dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */ umc_8886_ide_handler(1);
umc_8886_ide_handler(1);
} }
} }
static void static void
umc_8886_close(void *priv) umc_8886_close(void *priv)
{ {
@@ -257,7 +256,7 @@ umc_8886_init(const device_t *info)
umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t)); umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t));
memset(dev, 0, sizeof(umc_8886_t)); memset(dev, 0, sizeof(umc_8886_t));
dev->has_ide = (info->local && 0x886a); dev->has_ide = (info->local == 0x886a);
pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */ pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */
/* Add IDE if UM8886AF variant */ /* Add IDE if UM8886AF variant */