80486DX2-66/86Box-fork
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Reworked the CS8230 chipset using the 86box device model.

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This commit is contained in:
TC1995
2020-03-31 00:46:47 +02:00
parent cff4545082
commit 9cce85008a
1 changed files with 80 additions and 70 deletions
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150
src/chipset/cs8230.c
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@@ -30,17 +30,16 @@
#include <86box/chipset.h> #include <86box/chipset.h>
static struct typedef struct
{ {
int idx; int idx;
uint8_t regs[256]; uint8_t regs[256];
} cs8230; } cs8230_t;
static void shadow_control(uint32_t addr, uint32_t size, int state) static void
shadow_control(uint32_t addr, uint32_t size, int state)
{ {
// pclog("shadow_control: addr=%08x size=%04x state=%02x\n", addr, size, state); switch (state) {
switch (state)
{
case 0x00: case 0x00:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break; break;
@@ -58,88 +57,99 @@ static void shadow_control(uint32_t addr, uint32_t size, int state)
} }
static void rethink_shadow_mappings(void) static void
rethink_shadow_mappings(cs8230_t *cs8230)
{ {
int c; int c;
for (c = 0; c < 4*8; c++) /*Addresses 40000-bffff in 16k blocks*/ for (c = 0; c < 4*8; c++) { /*Addresses 40000-bffff in 16k blocks*/
{ if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7)))
if (cs8230.regs[0xa + (c >> 3)] & (1 << (c & 7))) mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/
mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ else
else mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/
mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/ }
} for (c = 0; c < 2*8; c++) { /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/
for (c = 0; c < 2*8; c++) /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/ if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7)))
{ mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/
if (cs8230.regs[0xe + (c >> 3)] & (1 << (c & 7))) else
mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230->regs[9] >> (3-(c >> 2))) & 0x11);
else }
shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230.regs[9] >> (3-(c >> 2))) & 0x11);
}
} }
static uint8_t cs8230_read(uint16_t port, void *p) static uint8_t
cs8230_read(uint16_t port, void *p)
{ {
cs8230_t *cs8230 = (cs8230_t *)p;
uint8_t ret = 0xff; uint8_t ret = 0xff;
if (port & 1) if (port & 1) {
{ switch (cs8230->idx) {
switch (cs8230.idx) case 0x04: /*82C301 ID/version*/
{ ret = cs8230->regs[cs8230->idx] & ~0xe3;
case 0x04: /*82C301 ID/version*/ break;
ret = cs8230.regs[cs8230.idx] & ~0xe3;
break;
case 0x08: /*82C302 ID/Version*/ case 0x08: /*82C302 ID/Version*/
ret = cs8230.regs[cs8230.idx] & ~0xe0; ret = cs8230->regs[cs8230->idx] & ~0xe0;
break; break;
case 0x05: case 0x06: /*82C301 registers*/ case 0x05: case 0x06: /*82C301 registers*/
case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/ case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/
case 0x0d: case 0x0e: case 0x0f: case 0x0d: case 0x0e: case 0x0f:
case 0x10: case 0x11: case 0x12: case 0x13: case 0x10: case 0x11: case 0x12: case 0x13:
case 0x28: case 0x29: case 0x2a: case 0x28: case 0x29: case 0x2a:
ret = cs8230.regs[cs8230.idx]; ret = cs8230->regs[cs8230->idx];
break; break;
} }
} }
return ret; return ret;
} }
static void cs8230_write(uint16_t port, uint8_t val, void *p) static void
cs8230_write(uint16_t port, uint8_t val, void *p)
{ {
if (!(port & 1)) cs8230_t *cs8230 = (cs8230_t *)p;
cs8230.idx = val;
else if (!(port & 1))
{ cs8230->idx = val;
// pclog("cs8230_write: reg=%02x val=%02x\n", cs8230.idx, val); else {
cs8230.regs[cs8230.idx] = val; cs8230->regs[cs8230->idx] = val;
switch (cs8230.idx) switch (cs8230->idx) {
{ case 0x09: /*RAM/ROM Configuration in boot area*/
case 0x09: /*RAM/ROM Configuration in boot area*/ case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/
case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/ rethink_shadow_mappings(cs8230);
// rethink_shadow_mappings(); break;
break; }
} }
}
} }
static void * cs8230_init(const device_t *info) static void
cs8230_close(void *priv)
{ {
memset(&cs8230, 0, sizeof(cs8230)); cs8230_t *cs8230 = (cs8230_t *)priv;
io_sethandler(0x0022, 0x0002, free(cs8230);
cs8230_read, NULL, NULL, }
cs8230_write, NULL, NULL,
NULL); static void
*cs8230_init(const device_t *info)
{
cs8230_t *cs8230 = (cs8230_t *)malloc(sizeof(cs8230_t));
memset(cs8230, 0, sizeof(cs8230_t));
io_sethandler(0x0022, 0x0002,
cs8230_read, NULL, NULL,
cs8230_write, NULL, NULL,
cs8230);
return cs8230;
} }
const device_t cs8230_device = { const device_t cs8230_device = {
"C&T CS8230 (386/AT)", "C&T CS8230 (386/AT)",
0, 0,
0, 0,
cs8230_init, NULL, NULL, cs8230_init, cs8230_close, NULL,
NULL, NULL, NULL, NULL, NULL, NULL,
NULL NULL
}; };