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Rewritten the PIIX IDE Bus Master operation, ReactOS now boots using IDE DMA and ATAPI DMA;

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Fixed the IDE device detection hang with > 8 GB hard disks;
Rewritten the SMC FDC37C932FR Super I/O chip emulation;
Added an early implementation of the PIIX4, currently not in the makefile because nothing uses it right now.
This commit is contained in:
OBattler
2017-10-26 20:37:39 +02:00
parent 4eba751cb0
commit 9ea0163bb7
11 changed files with 1264 additions and 777 deletions
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67
src/cdrom/cdrom.c
View File

@@ -9,7 +9,7 @@
* Implementation of the CD-ROM drive with SCSI(-like)
* commands, for both ATAPI and SCSI usage.
*
* Version: @(#)cdrom.c 1.0.19 2017/10/22
* Version: @(#)cdrom.c 1.0.20 2017/10/26
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
@@ -792,6 +792,12 @@ void build_scsi_cdrom_map()
}
}
void cdrom_set_callback(uint8_t id)
{
if (cdrom_drives[id].bus_type != CDROM_BUS_SCSI)
ide_set_callback(cdrom_drives[id].ide_channel, cdrom[id].callback);
}
void cdrom_set_cdb_len(int id, int cdb_len)
{
cdrom[id].cdb_len = cdb_len;
@@ -1288,16 +1294,23 @@ static void cdrom_command_common(uint8_t id)
cdrom[id].status = BUSY_STAT;
cdrom[id].phase = 1;
cdrom[id].pos = 0;
if (cdrom[id].packet_status == CDROM_PHASE_COMPLETE)
if (cdrom[id].packet_status == CDROM_PHASE_COMPLETE) {
cdrom[id].callback = 20LL * CDROM_TIME;
cdrom_set_callback(id);
}
else if (cdrom[id].packet_status == CDROM_PHASE_DATA_IN) {
if (cdrom[id].current_cdb[0] == 0x42) {
cdrom_log("CD-ROM %i: READ SUBCHANNEL\n");
cdrom[id].callback = 1000LL * CDROM_TIME;
} else
cdrom_set_callback(id);
} else {
cdrom[id].callback = 60LL * CDROM_TIME;
} else
cdrom_set_callback(id);
}
} else {
cdrom[id].callback = 60LL * CDROM_TIME;
cdrom_set_callback(id);
}
}
static void cdrom_command_complete(uint8_t id)
@@ -1400,6 +1413,7 @@ static void cdrom_cmd_error(uint8_t id)
cdrom[id].phase = 3;
cdrom[id].packet_status = 0x80;
cdrom[id].callback = 50LL * CDROM_TIME;
cdrom_set_callback(id);
cdrom_log("CD-ROM %i: ERROR: %02X/%02X/%02X\n", id, cdrom_sense_key, cdrom_asc, cdrom_ascq);
}
@@ -1413,9 +1427,16 @@ static void cdrom_unit_attention(uint8_t id)
cdrom[id].phase = 3;
cdrom[id].packet_status = 0x80;
cdrom[id].callback = 50LL * CDROM_TIME;
cdrom_set_callback(id);
cdrom_log("CD-ROM %i: UNIT ATTENTION\n", id);
}
static void cdrom_bus_master_error(uint8_t id)
{
cdrom_sense_key = cdrom_asc = cdrom_ascq = 0;
cdrom_cmd_error(id);
}
static void cdrom_not_ready(uint8_t id)
{
cdrom_sense_key = SENSE_NOT_READY;
@@ -1923,9 +1944,10 @@ void cdrom_clear_callback(uint8_t channel)
{
uint8_t id = atapi_cdrom_drives[channel];
if (id <= CDROM_NUM)
if (id < CDROM_NUM)
{
cdrom[id].callback = 0LL;
cdrom_set_callback(id);
}
}
@@ -1950,6 +1972,7 @@ void cdrom_reset(uint8_t id)
cdrom_rezero(id);
cdrom[id].status = 0;
cdrom[id].callback = 0LL;
cdrom_set_callback(id);
cdrom[id].packet_status = 0xff;
cdrom[id].unit_attention = 0;
}
@@ -2284,6 +2307,7 @@ cdrom_readtoc_fallback:
/* cdrom_log("CD-ROM %i: All done - callback set\n", id); */
cdrom[id].packet_status = CDROM_PHASE_COMPLETE;
cdrom[id].callback = 20LL * CDROM_TIME;
cdrom_set_callback(id);
break;
}
@@ -3032,12 +3056,12 @@ void cdrom_callback(uint8_t id) /* Callback for non-Read CD commands */
if (cdrom[id].pos >= cdrom[id].packet_len)
{
cdrom_log("CD-ROM %i: %i bytes read, command done\n", id, cdrom[id].total_read);
cdrom_log("CD-ROM %i: %i bytes read, command done\n", id, cdrom[id].pos);
cdrom[id].pos = cdrom[id].request_pos = 0;
cdrom_command_complete(id);
} else {
cdrom_log("CD-ROM %i: %i bytes read, %i bytes are still left\n", id, cdrom[id].total_read, cdrom[id].packet_len - cdrom[id].total_read);
cdrom_log("CD-ROM %i: %i bytes read, %i bytes are still left\n", id, cdrom[id].pos, cdrom[id].packet_len - cdrom[id].pos);
/* Make sure to keep pos, and reset request_pos to 0. */
/* Also make sure to not reset total_read. */
@@ -3096,13 +3120,13 @@ int cdrom_read_from_ide_dma(uint8_t channel)
if (ide_bus_master_write) {
if (ide_bus_master_write(channel >> 1, cdbufferb, cdrom[id].packet_len)) {
cdrom_data_phase_error(id);
cdrom_bus_master_error(id);
cdrom_phase_callback(id);
return 0;
} else
return 1;
} else {
cdrom_data_phase_error(id);
cdrom_bus_master_error(id);
cdrom_phase_callback(id);
return 0;
}
@@ -3166,20 +3190,27 @@ int cdrom_write_to_ide_dma(uint8_t channel)
{
uint8_t id = atapi_cdrom_drives[channel];
if (id > CDROM_NUM)
if (id > CDROM_NUM) {
cdrom_log("CD-ROM %i: Drive not found\n", id);
cdrom_data_phase_error(id);
cdrom_phase_callback(id);
return 0;
}
if (ide_bus_master_read) {
if (piix_bus_master_dma_read(channel >> 1, cdbufferb, cdrom[id].packet_len)) {
/* cdrom_log("CD-ROM %i: ATAPI DMA error\n", id); */
cdrom_data_phase_error(id);
if (ide_bus_master_read(channel >> 1, cdbufferb, cdrom[id].packet_len)) {
cdrom_log("CD-ROM %i: ATAPI DMA error\n", id);
cdrom_bus_master_error(id);
cdrom_phase_callback(id);
return 0;
}
else
else {
cdrom_log("CD-ROM %i: ATAPI DMA success\n", id);
return 1;
}
} else {
cdrom_data_phase_error(id);
cdrom_log("CD-ROM %i: No bus master\n", id);
cdrom_bus_master_error(id);
cdrom_phase_callback(id);
return 0;
}
@@ -3336,13 +3367,13 @@ uint32_t cdrom_read(uint8_t channel, int length)
if (cdrom[id].packet_status == CDROM_PHASE_DATA_IN) {
if ((cdrom[id].request_pos >= cdrom[id].request_length) || (cdrom[id].pos >= cdrom[id].packet_len)) {
/* Time for a DRQ. */
cdrom_log("CD-ROM %i: Issuing read callback\n", id);
// cdrom_log("CD-ROM %i: Issuing read callback\n", id);
cdrom_callback(id);
}
cdrom_log("CD-ROM %i: Returning: %02X (buffer position: %i, request position: %i)\n", id, temp, cdrom[id].pos, cdrom[id].request_pos);
// cdrom_log("CD-ROM %i: Returning: %02X (buffer position: %i, request position: %i)\n", id, temp, cdrom[id].pos, cdrom[id].request_pos);
return temp;
} else {
cdrom_log("CD-ROM %i: Returning zero (buffer position: %i, request position: %i)\n", id, cdrom[id].pos, cdrom[id].request_pos);
// cdrom_log("CD-ROM %i: Returning zero (buffer position: %i, request position: %i)\n", id, cdrom[id].pos, cdrom[id].request_pos);
return 0;
}
}

149
src/disk/hdc_ide.c
View File

@@ -9,7 +9,7 @@
* Implementation of the IDE emulation for hard disks and ATAPI
* CD-ROM devices.
*
* Version: @(#)hdc_ide.c 1.0.13 2017/10/16
* Version: @(#)hdc_ide.c 1.0.15 2017/10/26
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -24,6 +24,7 @@
#include <stdint.h>
#include <string.h>
#include <stdarg.h>
#include <inttypes.h>
#include <wchar.h>
#include "../86box.h"
#include "../ibm.h"
@@ -103,8 +104,7 @@ int cur_ide[5];
#ifdef ENABLE_IDE_LOG
// int ide_do_log = ENABLE_IDE_LOG;
int ide_do_log = 0;
int ide_do_log = ENABLE_IDE_LOG;
#endif
static void ide_log(const char *format, ...)
@@ -214,63 +214,6 @@ void ide_irq_lower(IDE *ide)
ide->irqstat=0;
}
void ide_irq_update(IDE *ide)
{
int pending = 0;
int mask = 0;
if (ide->board > 3)
{
return;
}
ide_log("Updating IRQ %i (board %i)\n", ide_irq[ide->board], ide->board);
mask = ide_irq[ide->board];
mask &= 7;
pending = (pic2.pend | pic2.ins);
pending &= (1 << mask);
if (ide->irqstat && !pending && !(ide->fdisk & 2))
{
if (pci_use_mirq(0) && (ide->board == 1))
{
pci_set_mirq(0);
}
else
{
picint(1 << ide_irq[ide->board]);
}
if (ide->board < 2)
{
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board | 0x40);
}
}
}
else if (pending)
{
if (pci_use_mirq(0) && (ide->board == 1))
{
pci_clear_mirq(0);
}
else
{
picintc(1 << ide_irq[ide->board]);
}
if (ide->board < 2)
{
if (ide_bus_master_set_irq)
{
ide_bus_master_set_irq(ide->board);
}
}
}
}
/**
* Copy a string into a buffer, padding with spaces, and placing characters as
* if they were packed into 16-bit values, stored little-endian.
@@ -357,26 +300,13 @@ static void ide_identify(IDE *ide)
ide->buffer[1] = d_tracks; /* Tracks in default CHS translation. */
ide->buffer[3] = d_hpc; /* Heads in default CHS translation. */
ide->buffer[6] = d_spt; /* Heads in default CHS translation. */
} else {
ide->buffer[1] = 16383; /* Tracks in default CHS translation. */
ide->buffer[3] = 16; /* Heads in default CHS translation. */
ide->buffer[6] = 63; /* Heads in default CHS translation. */
}
ide_log("Default CHS translation: %i, %i, %i\n", ide->buffer[1], ide->buffer[3], ide->buffer[6]);
#if 0
c = d_tracks; /* Cylinders */
h = d_hpc; /* Heads */
s = hdd[ide->hdd_num].spt; /* Sectors */
if (hdd[ide->hdd_num].tracks <= 16383)
{
ide->buffer[1] = hdd[ide->hdd_num].tracks; /* Cylinders */
}
else
{
ide->buffer[1] = 16383; /* Cylinders */
}
ide->buffer[3] = hdd[ide->hdd_num].hpc; /* Heads */
ide->buffer[6] = hdd[ide->hdd_num].spt; /* Sectors */
#endif
ide_padstr((char *) (ide->buffer + 10), "", 20); /* Serial Number */
ide_padstr((char *) (ide->buffer + 23), EMU_VERSION, 8); /* Firmware */
ide_padstr((char *) (ide->buffer + 27), device_identify, 40); /* Model */
@@ -393,6 +323,7 @@ static void ide_identify(IDE *ide)
if ((ide->tracks >= 1024) || (ide->hpc > 16) || (ide->spt > 63))
{
ide->buffer[49] |= (1 << 9);
ide_log("LBA supported\n");
}
ide->buffer[50] = 0x4000; /* Capabilities */
ide->buffer[51] = 2 << 8; /*PIO timing mode*/
@@ -401,26 +332,32 @@ static void ide_identify(IDE *ide)
{
ide->buffer[60] = full_size & 0xFFFF; /* Total addressable sectors (LBA) */
ide->buffer[61] = (full_size >> 16) & 0x0FFF;
ide_log("Full size: %" PRIu64 "\n", full_size);
ide->buffer[53] |= 1;
if (full_size <= 16514064) {
if (ide->specify_success) {
ide->buffer[54] = (full_size / ide->t_hpc) / ide->t_spt;
ide->buffer[55] = ide->t_hpc;
ide->buffer[56] = ide->t_spt;
full_size = ((uint64_t) ide->t_hpc) * ((uint64_t) ide->t_spt) * ((uint64_t) ide->buffer[54]);
} else {
if (ide->specify_success) {
ide->buffer[54] = (full_size / ide->t_hpc) / ide->t_spt;
ide->buffer[55] = ide->t_hpc;
ide->buffer[56] = ide->t_spt;
} else {
if (full_size <= 16514064) {
ide->buffer[54] = d_tracks;
ide->buffer[55] = d_hpc;
ide->buffer[56] = d_spt;
} else {
ide->buffer[54] = 16383;
ide->buffer[55] = 16;
ide->buffer[56] = 63;
}
ide->buffer[57] = full_size & 0xFFFF; /* Total addressable sectors (LBA) */
ide->buffer[58] = (full_size >> 16) & 0x0FFF;
ide_log("Current CHS translation: %i, %i, %i\n", ide->buffer[54], ide->buffer[55], ide->buffer[56]);
}
full_size = ((uint64_t) ide->buffer[54]) * ((uint64_t) ide->buffer[55]) * ((uint64_t) ide->buffer[56]);
ide->buffer[57] = full_size & 0xFFFF; /* Total addressable sectors (LBA) */
ide->buffer[58] = (full_size >> 16) & 0x0FFF;
ide_log("Current CHS translation: %i, %i, %i\n", ide->buffer[54], ide->buffer[55], ide->buffer[56]);
}
ide->buffer[59] = ide->blocksize ? (ide->blocksize | 0x100) : 0;
@@ -437,9 +374,9 @@ static void ide_identify(IDE *ide)
{
d = (ide->mdma_mode & 0xff);
d <<= 8;
if ((ide->mdma_mode & 0x100) == 0x200)
if ((ide->mdma_mode & 0x300) == 0x200)
ide->buffer[88] |= d;
else if ((ide->mdma_mode & 0x100) == 0x100)
else if ((ide->mdma_mode & 0x300) == 0x100)
ide->buffer[63] |= d;
else
ide->buffer[62] |= d;
@@ -490,9 +427,9 @@ static void ide_atapi_identify(IDE *ide)
{
d = (ide->mdma_mode & 0xff);
d <<= 8;
if ((ide->mdma_mode & 0x100) == 0x200)
if ((ide->mdma_mode & 0x300) == 0x200)
ide->buffer[88] |= d;
else if ((ide->mdma_mode & 0x100) == 0x100)
else if ((ide->mdma_mode & 0x300) == 0x100)
ide->buffer[63] |= d;
else
ide->buffer[62] |= d;
@@ -810,6 +747,15 @@ void ide_reset_hard(void)
int idetimes = 0;
void ide_set_callback(uint8_t channel, int64_t callback)
{
IDE *ide = &ide_drives[channel];
if (callback)
idecallback[ide->board] += callback;
else
idecallback[ide->board] = 0LL;
}
void ide_write_data(int ide_board, uint32_t val, int length)
{
IDE *ide = &ide_drives[cur_ide[ide_board]];
@@ -828,11 +774,6 @@ void ide_write_data(int ide_board, uint32_t val, int length)
}
cdrom_write(cur_ide[ide_board], val, length);
if (cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback)
{
idecallback[ide_board] = cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback;
}
return;
}
else
@@ -1026,7 +967,6 @@ void writeide(int ide_board, uint16_t addr, uint8_t val)
ide->lba_addr = (ide->lba_addr & 0x0FFFFFF) | ((val & 0xF) << 24);
ide_other->lba_addr = (ide_other->lba_addr & 0x0FFFFFF)|((val & 0xF) << 24);
ide_irq_update(ide);
return;
case 0x1F7: /* Command register */
@@ -1341,7 +1281,6 @@ ide_bad_command:
ide->atastat = ide_other->atastat = BUSY_STAT;
}
ide->fdisk = ide_other->fdisk = val;
ide_irq_update(ide);
return;
}
}
@@ -1364,10 +1303,6 @@ uint32_t ide_read_data(int ide_board, int length)
return 0;
}
temp = cdrom_read(cur_ide[ide_board], length);
if (cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback)
{
idecallback[ide_board] = cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback;
}
}
else
{
@@ -1616,11 +1551,6 @@ void callbackide(int ide_board)
}
ext_ide = ide;
if (ide_drive_is_cdrom(ide))
{
cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback = 0LL;
}
if (ide->command==0x30) times30++;
/*if (ide_board) */ide_log("CALLBACK %02X %i %i %i\n",ide->command,times30,ide->reset,cur_ide[ide_board]);
@@ -2143,7 +2073,6 @@ void callbackide(int ide_board)
}
cdrom_phase_callback(atapi_cdrom_drives[cur_ide[ide_board]]);
idecallback[ide_board] = cdrom[atapi_cdrom_drives[cur_ide[ide_board]]].callback;
ide_log("IDE callback now: %i\n", idecallback[ide_board]);
return;

7
src/disk/hdc_ide.h
View File

@@ -9,7 +9,7 @@
* Implementation of the IDE emulation for hard disks and ATAPI
* CD-ROM devices.
*
* Version: @(#)hdd_ide.h 1.0.4 2017/09/30
* Version: @(#)hdd_ide.h 1.0.5 2017/10/26
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -100,9 +100,14 @@ extern void ide_qua_enable(void);
extern void ide_qua_disable(void);
extern void ide_qua_init(void);
extern void ide_set_callback(uint8_t channel, int64_t callback);
extern void secondary_ide_check(void);
extern void ide_padstr8(uint8_t *buf, int buf_size, const char *src);
extern int (*ide_bus_master_read)(int channel, uint8_t *data, int transfer_length);
extern int (*ide_bus_master_write)(int channel, uint8_t *data, int transfer_length);
extern void (*ide_bus_master_set_irq)(int channel);
#endif /*EMU_IDE_H*/

181
src/piix.c
View File

@@ -162,6 +162,7 @@ void piix_write(int func, int addr, uint8_t val, void *priv)
else
pci_set_mirq_routing(PCI_MIRQ0, val & 0xf);
break;
pclog("MIRQ0 is %s\n", (val & 0x20) ? "disabled" : "enabled");
case 0x71:
if (piix_type == 1)
{
@@ -411,13 +412,19 @@ struct
int count;
uint32_t addr;
int eot;
uint8_t ptr0;
} piix_busmaster[2];
static void piix_bus_master_next_addr(int channel)
{
piix_busmaster[channel].addr = ((*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur])) & ~1) % (mem_size * 1024);
piix_busmaster[channel].count = (*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur + 4])) & 0xfffe;
piix_busmaster[channel].eot = (*(uint32_t *)(&ram[piix_busmaster[channel].ptr_cur + 4])) >> 31;
DMAPageRead(piix_busmaster[channel].ptr_cur, (char *) &(piix_busmaster[channel].addr), 4);
DMAPageRead(piix_busmaster[channel].ptr_cur + 4, (char *) &(piix_busmaster[channel].count), 4);
pclog("PIIX Bus master DWORDs: %08X %08X\n", piix_busmaster[channel].addr, piix_busmaster[channel].count);
piix_busmaster[channel].eot = piix_busmaster[channel].count >> 31;
piix_busmaster[channel].count &= 0xfffe;
if (!piix_busmaster[channel].count)
piix_busmaster[channel].count = 65536;
piix_busmaster[channel].addr &= 0xfffffffe;
piix_busmaster[channel].ptr_cur += 8;
}
@@ -425,37 +432,42 @@ void piix_bus_master_write(uint16_t port, uint8_t val, void *priv)
{
/* pclog("PIIX Bus master write: %04X %02X\n", port, val); */
int channel = (port & 8) ? 1 : 0;
switch (port & 7)
{
switch (port & 7) {
case 0:
if ((val & 1) && !(piix_busmaster[channel].command & 1)) /*Start*/
{
if ((val & 1) && !(piix_busmaster[channel].command & 1)) { /*Start*/
piix_busmaster[channel].ptr_cur = piix_busmaster[channel].ptr;
piix_bus_master_next_addr(channel);
piix_busmaster[channel].status |= 1;
}
if (!(val & 1) && (piix_busmaster[channel].command & 1)) /*Stop*/
if (!(val & 1) && (piix_busmaster[channel].command & 1)) /*Stop*/
piix_busmaster[channel].status &= ~1;
piix_busmaster[channel].command = val;
break;
case 2:
piix_busmaster[channel].status = (val & 0x60) | ((piix_busmaster[channel].status & ~val) & 6) | (piix_busmaster[channel].status & 1);
piix_busmaster[channel].status &= 0x07;
piix_busmaster[channel].status |= (val & 0x60);
if (val & 0x04)
piix_busmaster[channel].status &= ~0x04;
if (val & 0x02)
piix_busmaster[channel].status &= ~0x02;
/* piix_busmaster[channel].status = (val & 0x60) | ((piix_busmaster[channel].status & ~val) & 6) | (piix_busmaster[channel].status & 1); */
break;
case 4:
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffffff00) | val;
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffffff00) | (val & 0xfc);
piix_busmaster[channel].ptr %= (mem_size * 1024);
piix_busmaster[channel].ptr0 = val;
break;
case 5:
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffff00ff) | (val << 8);
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xffff00fc) | (val << 8);
piix_busmaster[channel].ptr %= (mem_size * 1024);
break;
case 6:
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xff00ffff) | (val << 16);
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0xff00fffc) | (val << 16);
piix_busmaster[channel].ptr %= (mem_size * 1024);
break;
case 7:
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0x00ffffff) | (val << 24);
piix_busmaster[channel].ptr = (piix_busmaster[channel].ptr & 0x00fffffc) | (val << 24);
piix_busmaster[channel].ptr %= (mem_size * 1024);
break;
@@ -466,14 +478,13 @@ uint8_t piix_bus_master_read(uint16_t port, void *priv)
{
/* pclog("PIIX Bus master read: %04X\n", port); */
int channel = (port & 8) ? 1 : 0;
switch (port & 7)
{
switch (port & 7) {
case 0:
return piix_busmaster[channel].command;
case 2:
return piix_busmaster[channel].status;
return piix_busmaster[channel].status & 0x67;
case 4:
return piix_busmaster[channel].ptr;
return piix_busmaster[channel].ptr0;
case 5:
return piix_busmaster[channel].ptr >> 8;
case 6:
@@ -496,78 +507,98 @@ int piix_bus_master_get_eot(int channel)
int piix_bus_master_dma_read(int channel, uint8_t *data, int transfer_length)
{
int transferred = 0;
int force_end = 0;
int buffer_pos = 0;
if (!(piix_busmaster[channel].status & 1))
return 1; /*DMA disabled*/
while (transferred < transfer_length)
{
mem_invalidate_range(piix_busmaster[channel].addr, piix_busmaster[channel].addr + transfer_length - 1);
if (piix_busmaster[channel].count < (transfer_length - transferred))
{
memcpy(&ram[piix_busmaster[channel].addr], data + transferred, piix_busmaster[channel].count);
transferred += piix_busmaster[channel].count;
piix_busmaster[channel].addr += piix_busmaster[channel].count;
piix_busmaster[channel].addr %= (mem_size * 1024);
piix_busmaster[channel].count = 0;
}
else
{
memcpy(&ram[piix_busmaster[channel].addr], data + transferred, transfer_length - transferred);
piix_busmaster[channel].addr += (transfer_length - transferred);
piix_busmaster[channel].count -= (transfer_length - transferred);
transferred += (transfer_length - transferred);
}
if (!piix_busmaster[channel].count)
{
if (piix_busmaster[channel].eot) /*End of transfer?*/
{
piix_busmaster[channel].status &= ~1;
}
else
piix_bus_master_next_addr(channel);
}
pclog("PIIX Bus master read: %i bytes\n", transfer_length);
while (1) {
if (piix_busmaster[channel].count <= transfer_length) {
pclog("Writing %i bytes to %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
DMAPageWrite(piix_busmaster[channel].addr, (char *) (data + buffer_pos), piix_busmaster[channel].count);
transfer_length -= piix_busmaster[channel].count;
buffer_pos += piix_busmaster[channel].count;
} else {
pclog("Writing %i bytes to %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
DMAPageWrite(piix_busmaster[channel].addr, (char *) (data + buffer_pos), transfer_length);
transfer_length = 0;
force_end = 1;
}
if (force_end) {
pclog("Total transfer length smaller than sum of all blocks, partial block\n");
piix_busmaster[channel].status &= ~2;
return 0; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
} else {
if (!transfer_length && !piix_busmaster[channel].eot) {
pclog("Total transfer length smaller than sum of all blocks, full block\n");
piix_busmaster[channel].status &= ~2;
return 0; /* We have exhausted the data to transfer but there's more blocks left, break. */
} else if (transfer_length && piix_busmaster[channel].eot) {
pclog("Total transfer length greater than sum of all blocks\n");
piix_busmaster[channel].status |= 2;
return 1; /* There is data left to transfer but we have reached EOT - return with error. */
} else if (piix_busmaster[channel].eot) {
pclog("Regular EOT\n");
piix_busmaster[channel].status &= ~3;
return 0; /* We have regularly reached EOT - clear status and break. */
} else {
/* We have more to transfer and there are blocks left, get next block. */
piix_bus_master_next_addr(channel);
}
}
}
return 0;
}
int piix_bus_master_dma_write(int channel, uint8_t *data, int transfer_length)
{
int transferred = 0;
int force_end = 0;
int buffer_pos = 0;
if (!(piix_busmaster[channel].status & 1))
return 1; /*DMA disabled*/
while (transferred < transfer_length)
{
if (piix_busmaster[channel].count < (transfer_length - transferred))
{
memcpy(data + transferred, &ram[piix_busmaster[channel].addr], piix_busmaster[channel].count);
transferred += piix_busmaster[channel].count;
piix_busmaster[channel].addr += piix_busmaster[channel].count;
piix_busmaster[channel].addr %= (mem_size * 1024);
piix_busmaster[channel].count = 0;
}
else
{
memcpy(data + transferred, &ram[piix_busmaster[channel].addr], transfer_length - transferred);
piix_busmaster[channel].addr += (transfer_length - transferred);
piix_busmaster[channel].count -= (transfer_length - transferred);
transferred += (transfer_length - transferred);
}
pclog("PIIX Bus master write: %i bytes\n", transfer_length);
if (!piix_busmaster[channel].count)
{
if (piix_busmaster[channel].eot) /*End of transfer?*/
{
piix_busmaster[channel].status &= ~1;
}
else
piix_bus_master_next_addr(channel);
}
while (1) {
if (piix_busmaster[channel].count <= transfer_length) {
pclog("Reading %i bytes from %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
DMAPageRead(piix_busmaster[channel].addr, (char *) (data + buffer_pos), piix_busmaster[channel].count);
transfer_length -= piix_busmaster[channel].count;
buffer_pos += piix_busmaster[channel].count;
} else {
pclog("Reading %i bytes from %08X\n", piix_busmaster[channel].count, piix_busmaster[channel].addr);
DMAPageRead(piix_busmaster[channel].addr, (char *) (data + buffer_pos), transfer_length);
transfer_length = 0;
force_end = 1;
}
if (force_end) {
pclog("Total transfer length smaller than sum of all blocks, partial block\n");
piix_busmaster[channel].status &= ~2;
return 0; /* This block has exhausted the data to transfer and it was smaller than the count, break. */
} else {
if (!transfer_length && !piix_busmaster[channel].eot) {
pclog("Total transfer length smaller than sum of all blocks, full block\n");
piix_busmaster[channel].status &= ~2;
return 0; /* We have exhausted the data to transfer but there's more blocks left, break. */
} else if (transfer_length && piix_busmaster[channel].eot) {
pclog("Total transfer length greater than sum of all blocks\n");
piix_busmaster[channel].status |= 2;
return 1; /* There is data left to transfer but we have reached EOT - return with error. */
} else if (piix_busmaster[channel].eot) {
pclog("Regular EOT\n");
piix_busmaster[channel].status &= ~3;
return 0; /* We have regularly reached EOT - clear status and break. */
} else {
/* We have more to transfer and there are blocks left, get next block. */
piix_bus_master_next_addr(channel);
}
}
}
return 0;
}

19
src/piix.h
View File

@@ -8,7 +8,7 @@
*
* Emulation core dispatcher.
*
* Version: @(#)piix.h 1.0.1 2017/08/23
* Version: @(#)piix.h 1.0.2 2017/10/25
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -16,13 +16,18 @@
* Copyright 2016,2017 Miran Grca.
*/
extern void piix_init(int card);
extern void piix_init(int card);
extern void piix3_init(int card);
extern void piix3_init(int card);
extern uint8_t piix_bus_master_read(uint16_t port, void *priv);
extern void piix_bus_master_write(uint16_t port, uint8_t val, void *priv);
extern void piix4_init(int card);
extern int piix_bus_master_get_count(int channel);
extern uint8_t piix_bus_master_read(uint16_t port, void *priv);
extern void piix_bus_master_write(uint16_t port, uint8_t val, void *priv);
extern int piix_bus_master_dma_read(int channel, uint8_t *data, int transfer_length);
extern int piix_bus_master_get_count(int channel);
extern int piix_bus_master_dma_read(int channel, uint8_t *data, int transfer_length);
extern int piix_bus_master_dma_write(int channel, uint8_t *data, int transfer_length);
extern void piix_bus_master_set_irq(int channel);

394
src/piix4.c Normal file
View File

@@ -0,0 +1,394 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* Preliminary emulation of the Intel PIIX4 Xcelerator.
*
* Emulation core dispatcher.
*
* PRD format :
* word 0 - base address
* word 1 - bits 1 - 15 = byte count, bit 31 = end of transfer
*
* Version: @(#)piix4.c 1.0.0 2017/10/25
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2017 Sarah Walker.
* Copyright 2016,2017 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "ibm.h"
#include "dma.h"
#include "io.h"
#include "device.h"
#include "keyboard_at.h"
#include "mem.h"
#include "pci.h"
#include "disk/hdc.h"
#include "disk/hdc_ide.h"
#include "piix.h"
static uint8_t card_piix4[256], card_piix4_ide[256];
static void piix4_write(int func, int addr, uint8_t val, void *priv)
{
uint16_t old_base = (card_piix4_ide[0x20] & 0xf0) | (card_piix4_ide[0x21] << 8);
if (func > 1)
return;
if (func == 1) /*IDE*/
{
/* pclog("PIIX IDE write: %02X %02X\n", addr, val); */
switch (addr)
{
case 0x04:
card_piix4_ide[0x04] = (val & 5) | 2;
break;
case 0x07:
card_piix4_ide[0x07] = val & 0x3e;
break;
case 0x0d:
card_piix4_ide[0x0d] = val;
break;
case 0x20:
card_piix4_ide[0x20] = (val & ~0x0f) | 1;
break;
case 0x21:
card_piix4_ide[0x21] = val;
break;
case 0x40:
card_piix4_ide[0x40] = val;
break;
case 0x41:
if ((val ^ card_piix4_ide[0x41]) & 0x80)
{
ide_pri_disable();
if (val & 0x80)
ide_pri_enable();
}
card_piix4_ide[0x41] = val;
break;
case 0x42:
card_piix4_ide[0x42] = val;
break;
case 0x43:
if ((val ^ card_piix4_ide[0x43]) & 0x80)
{
ide_sec_disable();
if (val & 0x80)
ide_sec_enable();
}
card_piix4_ide[0x43] = val;
break;
case 0x44:
card_piix4_ide[0x44] = val;
break;
case 0x48:
card_piix4_ide[0x44] = val;
break;
case 0x4A:
card_piix4_ide[0x44] = val;
break;
case 0x4B:
card_piix4_ide[0x44] = val;
break;
}
if (addr == 4 || (addr & ~3) == 0x20) /*Bus master base address*/
{
uint16_t base = (card_piix4_ide[0x20] & 0xf0) | (card_piix4_ide[0x21] << 8);
io_removehandler(old_base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
if (card_piix4_ide[0x04] & 1)
{
io_sethandler(base, 0x10, piix_bus_master_read, NULL, NULL, piix_bus_master_write, NULL, NULL, NULL);
}
}
}
else
{
/* pclog("PIIX writing value %02X to register %02X\n", val, addr); */
if ((addr >= 0x0f) && (addr < 0x4c))
return;
switch (addr)
{
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0e:
return;
case 0x60:
/* pclog("Set IRQ routing: INT A -> %02X\n", val); */
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTA, val & 0xf);
break;
case 0x61:
/* pclog("Set IRQ routing: INT B -> %02X\n", val); */
if (val & 0x80)
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTB, val & 0xf);
break;
case 0x62:
/* pclog("Set IRQ routing: INT C -> %02X\n", val); */
if (val & 0x80)
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTC, val & 0xf);
break;
case 0x63:
/* pclog("Set IRQ routing: INT D -> %02X\n", val); */
if (val & 0x80)
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
else
pci_set_irq_routing(PCI_INTD, val & 0xf);
break;
}
if (addr == 0x4C)
{
if (!((val ^ card_piix4[addr]) & 0x80))
{
card_piix4[addr] = val;
return;
}
card_piix4[addr] = val;
if (val & 0x80)
{
dma_alias_remove();
}
else
{
dma_alias_set();
}
}
else if (addr == 0x4E)
{
keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0);
card_piix4[addr] = val;
}
else
card_piix4[addr] = val;
}
}
static uint8_t piix4_read(int func, int addr, void *priv)
{
if (func > 1)
return 0xff;
if (func == 1) /*IDE*/
{
if (addr == 4)
{
return (card_piix4_ide[addr] & 5);
}
else if (addr == 5)
{
return 0;
}
else if (addr == 6)
{
return 0x80;
}
else if (addr == 7)
{
return card_piix4_ide[addr] & 0x3E;
}
else if (addr == 0xD)
{
return card_piix4_ide[addr] & 0xF0;
}
else if (addr == 0x20)
{
return (card_piix4_ide[addr] & 0xF0) | 1;
}
else if (addr == 0x22)
{
return 0;
}
else if (addr == 0x23)
{
return 0;
}
else if (addr == 0x41)
{
return card_piix4_ide[addr] & 0xF3;
}
else if (addr == 0x43)
{
return card_piix4_ide[addr] & 0xF3;
}
else if (addr == 0x48)
{
return card_piix4_ide[addr] & 0x0F;
}
else if (addr == 0x4A)
{
return card_piix4_ide[addr] & 0x33;
}
else if (addr == 0x4B)
{
return card_piix4_ide[addr] & 0x33;
}
else
{
return card_piix4_ide[addr];
}
}
else
{
if ((addr & 0xFC) == 0x60)
{
return card_piix4[addr] & 0x8F;
}
if (addr == 4)
{
return (card_piix4[addr] & 0x08) | 7;
}
else if (addr == 5)
{
return card_piix4[addr] & 0x01;
}
else if (addr == 6)
{
return 0x80;
}
else if (addr == 7)
{
return (card_piix4[addr] & 0x78) | 0x02;
}
else if (addr == 0x4E)
{
return (card_piix4[addr] & 0xEF) | keyboard_at_get_mouse_scan();
}
else if (addr == 0x4F)
{
return card_piix4[addr] & 0x06;
}
else if (addr == 0x69)
{
return card_piix4[addr] & 0xFE;
}
else if (addr == 0x6A)
{
return card_piix4[addr] & 0x80;
}
else if (addr == 0x6B)
{
return card_piix4[addr] & 0x80;
}
else if (addr == 0x76)
{
return (card_piix4[addr] & 0x87) | 0x08;
}
else if (addr == 0x77)
{
return (card_piix4[addr] & 0x87) | 0x08;
}
else if (addr == 0x80)
{
return card_piix4[addr] & 0x7F;
}
else if (addr == 0x82)
{
return card_piix4[addr] & 0x0F;
}
else if (addr == 0x91)
{
return card_piix4[addr] & 0xFC;
}
else if (addr == 0x92)
{
return card_piix4[addr] & 0xC0;
}
else if (addr == 0x94)
{
return card_piix4[addr] & 0xC0;
}
else if (addr == 0xB0)
{
return card_piix4[addr] & 0x7F;
}
else if (addr == 0xB1)
{
return card_piix4[addr] & 0xDF;
}
else if (addr == 0xB3)
{
return card_piix4[addr] & 0xFD;
}
else if (addr == 0xCB)
{
return card_piix4[addr] & 0x3D;
}
else
return card_piix4[addr];
}
return 0;
}
void piix4_reset(void)
{
memset(card_piix4, 0, 256);
memset(card_piix4_ide, 0, 256);
card_piix4[0x00] = 0x86; card_piix4[0x01] = 0x80; /*Intel*/
card_piix4[0x02] = 0x10; card_piix4[0x03] = 0x71; /*82371AB (PIIX4)*/
card_piix4[0x04] = 0x07; card_piix4[0x05] = 0x00;
card_piix4[0x06] = 0x80; card_piix4[0x07] = 0x02;
card_piix4[0x08] = 0x00; /*A0 stepping*/
card_piix4[0x09] = 0x00; card_piix4[0x0a] = 0x01; card_piix4[0x0b] = 0x06;
card_piix4[0x0e] = 0x80; /*Multi-function device*/
card_piix4[0x4c] = 0x4d;
card_piix4[0x4e] = 0x03;
card_piix4[0x60] = card_piix4[0x61] = card_piix4[0x62] = card_piix4[0x63] = 0x80;
card_piix4[0x64] = 0x10;
card_piix4[0x69] = 0x02;
card_piix4[0x76] = card_piix4[0x77] = 0x04;
card_piix4[0xcb] = 0x21;
card_piix4_ide[0x00] = 0x86; card_piix4_ide[0x01] = 0x80; /*Intel*/
card_piix4_ide[0x02] = 0x11; card_piix4_ide[0x03] = 0x71; /*82371AB (PIIX)*/
card_piix4_ide[0x04] = 0x07; card_piix4_ide[0x05] = 0x00;
card_piix4_ide[0x06] = 0x80; card_piix4_ide[0x07] = 0x02;
card_piix4_ide[0x08] = 0x00;
card_piix4_ide[0x09] = 0x80; card_piix4_ide[0x0a] = 0x01; card_piix4_ide[0x0b] = 0x01;
card_piix4_ide[0x0d] = 0x00;
card_piix4_ide[0x0e] = 0x00;
card_piix4_ide[0x20] = 0x01; card_piix4_ide[0x21] = card_piix4_ide[0x22] = card_piix4_ide[0x23] = 0x00; /*Bus master interface base address*/
card_piix4_ide[0x40] = card_piix4_ide[0x42] = 0x00;
card_piix4_ide[0x41] = card_piix4_ide[0x43] = 0x80;
}
void piix4_init(int card)
{
pci_add_card(card, piix4_read, piix4_write, NULL);
piix4_reset();
ide_set_bus_master(piix_bus_master_dma_read, piix_bus_master_dma_write, piix_bus_master_set_irq);
port_92_reset();
port_92_add();
dma_alias_set();
pci_reset_handler.pci_set_reset = piix4_reset;
}

4
src/sio.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the Super I/O chips.
*
* Version: @(#)sio.h 1.0.1 2017/09/03
* Version: @(#)sio.h 1.0.2 2017/10/26
*
* Author: Fred N. van Kempen, <decwiz@yahoo.com>
* Copyright 2017 Fred N. van Kempen.
@@ -18,9 +18,11 @@
extern void superio_detect_init(void);
extern void fdc37c663_init(void);
extern void fdc37c665_init(void);
extern void fdc37c669_init(void);
extern void fdc37c932fr_init(void);
extern void fdc37c935_init(void);
extern void pc87306_init(void);
extern void um8669f_init(void);
extern void w83877f_init(void);

113
src/sio_fdc37c665.c → src/sio_fdc37c66x.c
View File

@@ -6,9 +6,10 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C665 Super I/O Chip.
* Implementation of the SMC FDC37C663 and FDC37C665 Super
* I/O Chips.
*
* Version: @(#)sio_fdc37c665.c 1.0.7 2017/10/16
* Version: @(#)sio_fdc37c66x.c 1.0.8 2017/10/26
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -34,21 +35,21 @@
#include "sio.h"
static uint8_t fdc37c665_lock[2];
static int fdc37c665_curreg;
static uint8_t fdc37c665_regs[16];
static uint8_t fdc37c66x_lock[2];
static int fdc37c66x_curreg;
static uint8_t fdc37c66x_regs[16];
static int com3_addr, com4_addr;
static void write_lock(uint8_t val)
{
if (val == 0x55 && fdc37c665_lock[1] == 0x55)
if (val == 0x55 && fdc37c66x_lock[1] == 0x55)
fdc_3f1_enable(0);
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55 && val != 0x55)
if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55 && val != 0x55)
fdc_3f1_enable(1);
fdc37c665_lock[0] = fdc37c665_lock[1];
fdc37c665_lock[1] = val;
fdc37c66x_lock[0] = fdc37c66x_lock[1];
fdc37c66x_lock[1] = val;
}
static void ide_handler()
@@ -60,9 +61,9 @@ static void ide_handler()
return;
}
ide_pri_disable();
if (fdc37c665_regs[0] & 1)
if (fdc37c66x_regs[0] & 1)
{
if (fdc37c665_regs[5] & 2)
if (fdc37c66x_regs[5] & 2)
{
or_value = 0;
}
@@ -79,7 +80,7 @@ static void ide_handler()
static void set_com34_addr()
{
switch (fdc37c665_regs[1] & 0x60)
switch (fdc37c66x_regs[1] & 0x60)
{
case 0x00:
com3_addr = 0x338;
@@ -100,11 +101,11 @@ static void set_com34_addr()
}
}
void set_serial1_addr()
static void set_serial1_addr()
{
if (fdc37c665_regs[2] & 4)
if (fdc37c66x_regs[2] & 4)
{
switch (fdc37c665_regs[2] & 3)
switch (fdc37c66x_regs[2] & 3)
{
case 0:
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
@@ -125,11 +126,11 @@ void set_serial1_addr()
}
}
void set_serial2_addr()
static void set_serial2_addr()
{
if (fdc37c665_regs[2] & 0x40)
if (fdc37c66x_regs[2] & 0x40)
{
switch (fdc37c665_regs[2] & 0x30)
switch (fdc37c66x_regs[2] & 0x30)
{
case 0:
serial_setup(2, SERIAL1_ADDR, SERIAL1_IRQ);
@@ -153,7 +154,7 @@ void set_serial2_addr()
static void lpt1_handler()
{
lpt1_remove();
switch (fdc37c665_regs[1] & 3)
switch (fdc37c66x_regs[1] & 3)
{
case 1:
lpt1_init(0x3bc);
@@ -167,38 +168,38 @@ static void lpt1_handler()
}
}
void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
static void fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t valxor = 0;
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55)
{
if (port == 0x3f0)
{
if (val == 0xaa)
write_lock(val);
else
fdc37c665_curreg = val;
fdc37c66x_curreg = val;
#if 0
if (fdc37c665_curreg != 0)
if (fdc37c66x_curreg != 0)
{
fdc37c665_curreg = val & 0xf;
fdc37c66x_curreg = val & 0xf;
}
else
{
/* Hardcode the IDE to AT type. */
fdc37c665_curreg = (val & 0xf) | 2;
fdc37c66x_curreg = (val & 0xf) | 2;
}
#endif
}
else
{
if (fdc37c665_curreg > 15)
if (fdc37c66x_curreg > 15)
return;
valxor = val ^ fdc37c665_regs[fdc37c665_curreg];
fdc37c665_regs[fdc37c665_curreg] = val;
valxor = val ^ fdc37c66x_regs[fdc37c66x_curreg];
fdc37c66x_regs[fdc37c66x_curreg] = val;
switch(fdc37c665_curreg)
switch(fdc37c66x_curreg)
{
case 0:
if (valxor & 1)
@@ -234,7 +235,7 @@ void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
case 3:
if (valxor & 2)
{
fdc_update_enh_mode((fdc37c665_regs[3] & 2) ? 1 : 0);
fdc_update_enh_mode((fdc37c66x_regs[3] & 2) ? 1 : 0);
}
break;
case 5:
@@ -244,11 +245,11 @@ void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
}
if (valxor & 0x18)
{
fdc_update_densel_force((fdc37c665_regs[5] & 0x18) >> 3);
fdc_update_densel_force((fdc37c66x_regs[5] & 0x18) >> 3);
}
if (valxor & 0x20)
{
fdd_swap = ((fdc37c665_regs[5] & 0x20) >> 5);
fdd_swap = ((fdc37c66x_regs[5] & 0x20) >> 5);
}
break;
}
@@ -261,17 +262,17 @@ void fdc37c665_write(uint16_t port, uint8_t val, void *priv)
}
}
uint8_t fdc37c665_read(uint16_t port, void *priv)
static uint8_t fdc37c66x_read(uint16_t port, void *priv)
{
if (fdc37c665_lock[0] == 0x55 && fdc37c665_lock[1] == 0x55)
if (fdc37c66x_lock[0] == 0x55 && fdc37c66x_lock[1] == 0x55)
{
if (port == 0x3f1)
return fdc37c665_regs[fdc37c665_curreg];
return fdc37c66x_regs[fdc37c66x_curreg];
}
return 0xff;
}
void fdc37c665_reset(void)
static void fdc37c66x_reset(void)
{
com3_addr = 0x338;
com4_addr = 0x238;
@@ -292,24 +293,44 @@ void fdc37c665_reset(void)
lpt1_remove();
lpt1_init(0x378);
memset(fdc37c665_lock, 0, 2);
memset(fdc37c665_regs, 0, 16);
fdc37c665_regs[0x0] = 0x3a;
fdc37c665_regs[0x1] = 0x9f;
fdc37c665_regs[0x2] = 0xdc;
fdc37c665_regs[0x3] = 0x78;
fdc37c665_regs[0x6] = 0xff;
fdc37c665_regs[0xd] = 0x65;
fdc37c665_regs[0xe] = 0x01;
memset(fdc37c66x_lock, 0, 2);
memset(fdc37c66x_regs, 0, 16);
fdc37c66x_regs[0x0] = 0x3a;
fdc37c66x_regs[0x1] = 0x9f;
fdc37c66x_regs[0x2] = 0xdc;
fdc37c66x_regs[0x3] = 0x78;
fdc37c66x_regs[0x6] = 0xff;
fdc37c66x_regs[0xe] = 0x01;
fdc_update_densel_polarity(1);
fdc_update_densel_force(0);
fdd_swap = 0;
}
static void fdc37c663_reset(void)
{
fdc37c66x_reset();
fdc37c66x_regs[0xd] = 0x63;
}
static void fdc37c665_reset(void)
{
fdc37c66x_reset();
fdc37c66x_regs[0xd] = 0x65;
}
void fdc37c663_init()
{
io_sethandler(0x03f0, 0x0002, fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, NULL);
fdc37c663_reset();
pci_reset_handler.super_io_reset = fdc37c663_reset;
}
void fdc37c665_init()
{
io_sethandler(0x03f0, 0x0002, fdc37c665_read, NULL, NULL, fdc37c665_write, NULL, NULL, NULL);
io_sethandler(0x03f0, 0x0002, fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, NULL);
fdc37c665_reset();

516
src/sio_fdc37c932fr.c
View File

@@ -1,516 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C932FR Super I/O Chip.
*
* Version: @(#)sio_fdc37c932fr.c 1.0.6 2017/10/16
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "ibm.h"
#include "io.h"
#include "device.h"
#include "lpt.h"
#include "serial.h"
#include "disk/hdc.h"
#include "disk/hdc_ide.h"
#include "floppy/floppy.h"
#include "floppy/fdc.h"
#include "floppy/fdd.h"
#include "sio.h"
static int fdc37c932fr_locked;
static int fdc37c932fr_curreg = 0;
static int fdc37c932fr_gpio_curreg = 0;
static uint8_t fdc37c932fr_regs[48];
static uint8_t fdc37c932fr_ld_regs[10][256];
static uint8_t fdc37c932fr_gpio_regs[16] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
static uint8_t tries;
static uint16_t ld0_valid_ports[2] = {0x3F0, 0x370};
static uint16_t ld1_valid_ports[2] = {0x1F0, 0x170};
static uint16_t ld1_valid_ports2[2] = {0x3F6, 0x376};
static uint16_t ld2_valid_ports[2] = {0x170, 0x1F0};
static uint16_t ld2_valid_ports2[2] = {0x376, 0x3F6};
static uint16_t ld3_valid_ports[3] = {0x3BC, 0x378, 0x278};
static uint16_t ld4_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint16_t ld5_valid_ports[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint16_t ld5_valid_ports2[9] = {0x3F8, 0x2F8, 0x338, 0x3E8, 0x2E8, 0x220, 0x238, 0x2E0, 0x228};
static uint8_t is_in_array(uint16_t *port_array, uint8_t max, uint16_t port)
{
uint8_t i = 0;
for (i = 0; i < max; i++)
{
if (port_array[i] == port) return 1;
}
return 0;
}
static uint16_t make_port(uint8_t ld)
{
uint16_t r0 = fdc37c932fr_ld_regs[ld][0x60];
uint16_t r1 = fdc37c932fr_ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
switch(ld)
{
case 0:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F0;
if (!(is_in_array(ld0_valid_ports, 2, p))) p = 0x3F0;
break;
case 1:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x1F0;
if (!(is_in_array(ld1_valid_ports, 2, p))) p = 0x1F0;
break;
case 2:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x170;
if (!(is_in_array(ld2_valid_ports, 2, p))) p = 0x170;
break;
case 3:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x378;
if (!(is_in_array(ld3_valid_ports, 3, p))) p = 0x378;
break;
case 4:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F8;
if (!(is_in_array(ld4_valid_ports, 9, p))) p = 0x3F8;
break;
case 5:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x2F8;
if (!(is_in_array(ld5_valid_ports, 9, p))) p = 0x2F8;
break;
}
fdc37c932fr_ld_regs[ld][0x60] = (p >> 8);
fdc37c932fr_ld_regs[ld][0x61] = (p & 0xFF);
return p;
}
uint16_t make_port2(uint8_t ld)
{
uint16_t r0 = fdc37c932fr_ld_regs[ld][0x62];
uint16_t r1 = fdc37c932fr_ld_regs[ld][0x63];
uint16_t p = (r0 << 8) + r1;
switch(ld)
{
case 1:
p &= 0xFFF;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3F6;
if (!(is_in_array(ld1_valid_ports2, 2, p))) p = 0x3F6;
break;
case 2:
p &= 0xFFF;
if ((p < 0x100) || (p > 0xFF8)) p = 0x376;
if (!(is_in_array(ld2_valid_ports2, 2, p))) p = 0x376;
break;
case 5:
p &= 0xFF8;
if ((p < 0x100) || (p > 0xFF8)) p = 0x3E8;
if (!(is_in_array(ld5_valid_ports2, 9, p))) p = 0x3E8;
break;
}
fdc37c932fr_ld_regs[ld][0x62] = (p >> 8);
fdc37c932fr_ld_regs[ld][0x63] = (p & 0xFF);
return p;
}
void fdc37c932fr_gpio_write(uint16_t port, uint8_t val, void *priv)
{
if (port & 1)
{
if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg] = val;
}
else
{
fdc37c932fr_gpio_curreg = val;
}
}
void fdc37c932fr_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0;
uint16_t ld_port = 0;
if (index)
{
if ((val == 0x55) && !fdc37c932fr_locked)
{
if (tries)
{
fdc37c932fr_locked = 1;
fdc_3f1_enable(0);
tries = 0;
}
else
{
tries++;
}
}
else
{
if (fdc37c932fr_locked)
{
if (val == 0xaa)
{
fdc37c932fr_locked = 0;
fdc_3f1_enable(1);
return;
}
fdc37c932fr_curreg = val;
}
else
{
if (tries)
tries = 0;
}
}
}
else
{
if (fdc37c932fr_locked)
{
if (fdc37c932fr_curreg < 48)
{
valxor = val ^ fdc37c932fr_regs[fdc37c932fr_curreg];
fdc37c932fr_regs[fdc37c932fr_curreg] = val;
}
else
{
valxor = val ^ fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
if (((fdc37c932fr_curreg & 0xF0) == 0x70) && (fdc37c932fr_regs[7] < 4)) return;
/* Block writes to IDE configuration. */
if (fdc37c932fr_regs[7] == 1) return;
if (fdc37c932fr_regs[7] == 2) return;
if (fdc37c932fr_regs[7] > 5) return;
fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg] = val;
goto process_value;
}
}
}
return;
process_value:
switch(fdc37c932fr_regs[7])
{
case 0:
/* FDD */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
fdc_remove();
else
{
fdc_add();
}
}
break;
case 0x60:
case 0x61:
if (valxor && fdc37c932fr_ld_regs[0][0x30])
{
fdc_remove();
ld_port = make_port(0);
fdc37c932fr_ld_regs[0][0x60] = make_port(0) >> 8;
fdc37c932fr_ld_regs[0][0x61] = make_port(0) & 0xFF;
fdc_add();
}
break;
case 0xF0:
if (valxor & 0x01) fdc_update_enh_mode(val & 0x01);
if (valxor & 0x10) fdd_swap = ((val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC) fdc_update_densel_force((val & 0xC) >> 2);
break;
case 0xF2:
if (valxor & 0xC0) fdc_update_rwc(3, (valxor & 0xC0) >> 6);
if (valxor & 0x30) fdc_update_rwc(2, (valxor & 0x30) >> 4);
if (valxor & 0x0C) fdc_update_rwc(1, (valxor & 0x0C) >> 2);
if (valxor & 0x03) fdc_update_rwc(0, (valxor & 0x03));
break;
case 0xF4:
if (valxor & 0x18) fdc_update_drvrate(0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18) fdc_update_drvrate(1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18) fdc_update_drvrate(2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18) fdc_update_drvrate(3, (val & 0x18) >> 3);
break;
}
break;
case 3:
/* Parallel port */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
lpt1_remove();
else
{
ld_port = make_port(3);
lpt1_init(ld_port);
}
}
break;
case 0x60:
case 0x61:
if (valxor && fdc37c932fr_ld_regs[3][0x30])
{
lpt1_remove();
ld_port = make_port(3);
lpt1_init(ld_port);
}
break;
}
break;
case 4:
/* Serial port 1 */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
serial_remove(1);
else
{
ld_port = make_port(4);
serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
}
}
break;
case 0x60:
case 0x61:
case 0x70:
if (valxor && fdc37c932fr_ld_regs[4][0x30])
{
ld_port = make_port(4);
serial_setup(1, ld_port, fdc37c932fr_ld_regs[4][0x70]);
}
break;
}
break;
case 5:
/* Serial port 2 */
switch(fdc37c932fr_curreg)
{
case 0x30:
/* Activate */
if (valxor)
{
if (!val)
serial_remove(2);
else
{
ld_port = make_port(5);
serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
}
}
break;
case 0x60:
case 0x61:
case 0x70:
if (valxor && fdc37c932fr_ld_regs[5][0x30])
{
ld_port = make_port(5);
serial_setup(2, ld_port, fdc37c932fr_ld_regs[5][0x70]);
}
break;
}
break;
}
}
uint8_t fdc37c932fr_gpio_read(uint16_t port, void *priv)
{
if (port & 1)
{
if (fdc37c932fr_gpio_curreg && (fdc37c932fr_gpio_curreg <= 0xF))
return fdc37c932fr_gpio_regs[fdc37c932fr_gpio_curreg];
else
return 0xff;
}
else
{
return fdc37c932fr_gpio_curreg;
}
}
uint8_t fdc37c932fr_read(uint16_t port, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
if (!fdc37c932fr_locked)
{
return 0xff;
}
if (index)
return fdc37c932fr_curreg;
else
{
if (fdc37c932fr_curreg < 0x30)
{
return fdc37c932fr_regs[fdc37c932fr_curreg];
}
else
{
if ((fdc37c932fr_regs[7] == 0) && (fdc37c932fr_curreg == 0xF2)) return (fdc_get_rwc(0) | (fdc_get_rwc(1) << 2));
return fdc37c932fr_ld_regs[fdc37c932fr_regs[7]][fdc37c932fr_curreg];
}
}
}
void fdc37c932fr_reset(void)
{
int i = 0;
fdc37c932fr_regs[3] = 3;
fdc37c932fr_regs[0x20] = 3;
fdc37c932fr_regs[0x21] = 1;
fdc37c932fr_regs[0x24] = 4;
fdc37c932fr_regs[0x26] = 0xF0;
fdc37c932fr_regs[0x27] = 3;
for (i = 0; i < 10; i++)
{
memset(fdc37c932fr_ld_regs[i], 0, 256);
}
/* Logical device 0: FDD */
fdc37c932fr_ld_regs[0][0x30] = 1;
fdc37c932fr_ld_regs[0][0x60] = 3;
fdc37c932fr_ld_regs[0][0x61] = 0xF0;
fdc37c932fr_ld_regs[0][0x70] = 6;
fdc37c932fr_ld_regs[0][0x74] = 2;
fdc37c932fr_ld_regs[0][0xF0] = 0xE;
fdc37c932fr_ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
fdc37c932fr_ld_regs[1][0x30] = 0;
fdc37c932fr_ld_regs[1][0x60] = 1;
fdc37c932fr_ld_regs[1][0x61] = 0xF0;
fdc37c932fr_ld_regs[1][0x62] = 3;
fdc37c932fr_ld_regs[1][0x63] = 0xF6;
fdc37c932fr_ld_regs[1][0x70] = 0xE;
fdc37c932fr_ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
fdc37c932fr_ld_regs[2][0x30] = 0;
fdc37c932fr_ld_regs[2][0x60] = 1;
fdc37c932fr_ld_regs[2][0x61] = 0x70;
fdc37c932fr_ld_regs[2][0x62] = 3;
fdc37c932fr_ld_regs[2][0x63] = 0x76;
fdc37c932fr_ld_regs[2][0x70] = 0xF;
/* Logical device 3: Parallel Port */
fdc37c932fr_ld_regs[3][0x30] = 1;
fdc37c932fr_ld_regs[3][0x60] = 3;
fdc37c932fr_ld_regs[3][0x61] = 0x78;
fdc37c932fr_ld_regs[3][0x70] = 7;
fdc37c932fr_ld_regs[3][0x74] = 4;
fdc37c932fr_ld_regs[3][0xF0] = 0x3C;
/* Logical device 4: Serial Port 1 */
fdc37c932fr_ld_regs[4][0x30] = 1;
fdc37c932fr_ld_regs[4][0x60] = 3;
fdc37c932fr_ld_regs[4][0x61] = 0xf8;
fdc37c932fr_ld_regs[4][0x70] = 4;
fdc37c932fr_ld_regs[4][0xF0] = 3;
serial_setup(1, 0x3f8, fdc37c932fr_ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
fdc37c932fr_ld_regs[5][0x30] = 1;
fdc37c932fr_ld_regs[5][0x60] = 2;
fdc37c932fr_ld_regs[5][0x61] = 0xf8;
fdc37c932fr_ld_regs[5][0x70] = 3;
fdc37c932fr_ld_regs[5][0x74] = 4;
fdc37c932fr_ld_regs[5][0xF1] = 2;
fdc37c932fr_ld_regs[5][0xF2] = 3;
serial_setup(2, 0x2f8, fdc37c932fr_ld_regs[5][0x70]);
/* Logical device 6: RTC */
fdc37c932fr_ld_regs[6][0x63] = 0x70;
fdc37c932fr_ld_regs[6][0xF4] = 3;
/* Logical device 7: Keyboard */
fdc37c932fr_ld_regs[7][0x30] = 1;
fdc37c932fr_ld_regs[7][0x61] = 0x60;
fdc37c932fr_ld_regs[7][0x70] = 1;
/* Logical device 8: AUX I/O */
/* Logical device 9: ACCESS.bus */
fdc_update_densel_force(0);
fdd_swap = 0;
fdc_update_rwc(0, 0);
fdc_update_rwc(1, 0);
fdc_update_rwc(2, 0);
fdc_update_rwc(3, 0);
fdc_update_drvrate(0, 0);
fdc_update_drvrate(1, 0);
fdc_update_drvrate(2, 0);
fdc_update_drvrate(3, 0);
fdc_update_max_track(79);
memset(fdc37c932fr_gpio_regs, 0, sizeof(fdc37c932fr_gpio_regs));
fdc37c932fr_gpio_regs[2] = 0xfd;
fdc37c932fr_locked = 0;
}
void fdc37c932fr_init()
{
lpt2_remove();
fdc37c932fr_reset();
io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xe2, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xe4, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
io_sethandler(0x3f0, 0x0002, fdc37c932fr_read, NULL, NULL, fdc37c932fr_write, NULL, NULL, NULL);
pci_reset_handler.super_io_reset = fdc37c932fr_reset;
}

582
src/sio_fdc37c93x.c Normal file
View File

@@ -0,0 +1,582 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C932FR and FDC37C935 Super
* I/O Chips.
*
* Version: @(#)sio_fdc37c93x.c 1.0.7 2017/10/26
*
* Author: Miran Grca, <mgrca8@gmail.com>
* Copyright 2016,2017 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "ibm.h"
#include "io.h"
#include "device.h"
#include "lpt.h"
#include "serial.h"
#include "disk/hdc.h"
#include "disk/hdc_ide.h"
#include "floppy/floppy.h"
#include "floppy/fdc.h"
#include "floppy/fdd.h"
#include "sio.h"
static int fdc37c93x_locked;
static int fdc37c93x_curreg = 0;
static int fdc37c93x_gpio_reg = 0;
static uint8_t fdc37c93x_regs[48];
static uint8_t fdc37c93x_ld_regs[10][256];
static uint8_t fdc37c93x_gpio_base = 0x00EA;
static uint8_t tries;
static uint16_t make_port(uint8_t ld)
{
uint16_t r0 = fdc37c93x_ld_regs[ld][0x60];
uint16_t r1 = fdc37c93x_ld_regs[ld][0x61];
uint16_t p = (r0 << 8) + r1;
return p;
}
static uint8_t fdc37c93x_gpio_read(uint16_t port, void *priv)
{
pclog("fdc37c93x: GPIO read: %02X\n", fdc37c93x_gpio_reg);
return fdc37c93x_gpio_reg;
}
static void fdc37c93x_gpio_write(uint16_t port, uint8_t val, void *priv)
{
pclog("fdc37c93x: GPIO write: %02X\n", val);
fdc37c93x_gpio_reg = val;
}
static void fdc37c93x_fdc_handler(void)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 0));
uint8_t local_enable = !!fdc37c93x_ld_regs[0][0x30];
fdc_remove();
if (global_enable && local_enable)
{
ld_port = make_port(0);
pclog("fdc37c93x: Setting FDC port to %04X\n", ld_port);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8)) {
fdc_set_base(ld_port, 1);
}
}
}
static void fdc37c93x_lpt_handler(void)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 3));
uint8_t local_enable = !!fdc37c93x_ld_regs[3][0x30];
lpt1_remove();
if (global_enable && local_enable)
{
ld_port = make_port(3);
pclog("fdc37c93x: Setting LPT1 port to %04X\n", ld_port);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
lpt1_init(ld_port);
}
}
static void fdc37c93x_serial_handler(int uart)
{
uint16_t ld_port = 0;
uint8_t uart_no = 3 + uart;
uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << uart_no));
uint8_t local_enable = !!fdc37c93x_ld_regs[uart_no][0x30];
serial_remove(uart);
if (global_enable && local_enable)
{
ld_port = make_port(uart_no);
pclog("fdc37c93x: Setting COM%i port to %04X\n", uart, ld_port);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FF8))
serial_setup(uart, ld_port, fdc37c93x_ld_regs[uart_no][0x70]);
}
}
static void fdc37c93x_auxio_handler(void)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 3));
uint8_t local_enable = !!fdc37c93x_ld_regs[3][0x30];
io_removehandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
if (global_enable && local_enable)
{
fdc37c93x_gpio_base = ld_port = make_port(3);
pclog("fdc37c93x: Setting Auxiliary I/O port to %04X\n", ld_port);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFF))
io_sethandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
}
}
#define AB_RST 0x80
typedef struct {
uint8_t control;
uint8_t status;
uint8_t own_addr;
uint8_t data;
uint8_t clock;
uint16_t base;
} access_bus_t;
static access_bus_t access_bus;
static uint8_t fdc37c932fr_access_bus_read(uint16_t port, void *priv)
{
switch(port & 3) {
case 0:
return (access_bus.status & 0xBF);
break;
case 1:
return (access_bus.own_addr & 0x7F);
break;
case 2:
return access_bus.data;
break;
case 3:
return (access_bus.clock & 0x87);
break;
default:
return 0xFF;
}
}
static void fdc37c932fr_access_bus_write(uint16_t port, uint8_t val, void *priv)
{
switch(port & 3) {
case 0:
access_bus.control = (val & 0xCF);
break;
case 1:
access_bus.own_addr = (val & 0x7F);
break;
case 2:
access_bus.data = val;
break;
case 3:
access_bus.clock &= 0x80;
access_bus.clock |= (val & 0x07);
break;
}
}
static void fdc37c932fr_access_bus_handler(void)
{
uint16_t ld_port = 0;
uint8_t global_enable = !!(fdc37c93x_regs[0x22] & (1 << 6));
uint8_t local_enable = !!fdc37c93x_ld_regs[9][0x30];
io_removehandler(access_bus.base, 0x0004, fdc37c932fr_access_bus_read, NULL, NULL, fdc37c932fr_access_bus_write, NULL, NULL, NULL);
if (global_enable && local_enable)
{
access_bus.base = ld_port = make_port(9);
pclog("fdc37c93x: Setting Auxiliary I/O port to %04X\n", ld_port);
if ((ld_port >= 0x0100) && (ld_port <= 0x0FFC))
io_sethandler(access_bus.base, 0x0004, fdc37c932fr_access_bus_read, NULL, NULL, fdc37c932fr_access_bus_write, NULL, NULL, NULL);
}
}
static void fdc37c93x_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor = 0;
if (index)
{
if ((val == 0x55) && !fdc37c93x_locked)
{
if (tries)
{
fdc37c93x_locked = 1;
fdc_3f1_enable(0);
tries = 0;
}
else
{
tries++;
}
}
else
{
if (fdc37c93x_locked)
{
if (val == 0xaa)
{
fdc37c93x_locked = 0;
fdc_3f1_enable(1);
return;
}
fdc37c93x_curreg = val;
}
else
{
if (tries)
tries = 0;
}
}
}
else
{
if (fdc37c93x_locked)
{
if (fdc37c93x_curreg < 48)
{
valxor = val ^ fdc37c93x_regs[fdc37c93x_curreg];
if ((val == 0x20) || (val == 0x21))
return;
fdc37c93x_regs[fdc37c93x_curreg] = val;
goto process_value;
}
else
{
valxor = val ^ fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg];
if (((fdc37c93x_curreg & 0xF0) == 0x70) && (fdc37c93x_regs[7] < 4)) return;
/* Block writes to IDE configuration. */
if (fdc37c93x_regs[7] == 1) return;
if (fdc37c93x_regs[7] == 2) return;
if ((fdc37c93x_regs[7] > 5) && (fdc37c93x_regs[7] != 8) && (fdc37c93x_regs[7] != 9)) return;
if ((fdc37c93x_regs[7] == 9) && (fdc37c93x_regs[0x20] != 3)) return;
fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg] = val;
goto process_value;
}
}
}
return;
process_value:
if (fdc37c93x_curreg < 48)
{
switch(fdc37c93x_curreg)
{
case 0x22:
if (valxor & 0x01)
fdc37c93x_fdc_handler();
if (valxor & 0x08)
fdc37c93x_lpt_handler();
if (valxor & 0x10)
fdc37c93x_serial_handler(1);
if (valxor & 0x20)
fdc37c93x_serial_handler(2);
break;
}
return;
}
switch(fdc37c93x_regs[7])
{
case 0:
/* FDD */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
if (valxor)
{
fdc37c93x_fdc_handler();
}
break;
case 0xF0:
if (valxor & 0x01) fdc_update_enh_mode(val & 0x01);
if (valxor & 0x10) fdd_swap = ((val & 0x10) >> 4);
break;
case 0xF1:
if (valxor & 0xC) fdc_update_densel_force((val & 0xC) >> 2);
break;
case 0xF2:
if (valxor & 0xC0) fdc_update_rwc(3, (valxor & 0xC0) >> 6);
if (valxor & 0x30) fdc_update_rwc(2, (valxor & 0x30) >> 4);
if (valxor & 0x0C) fdc_update_rwc(1, (valxor & 0x0C) >> 2);
if (valxor & 0x03) fdc_update_rwc(0, (valxor & 0x03));
break;
case 0xF4:
if (valxor & 0x18) fdc_update_drvrate(0, (val & 0x18) >> 3);
break;
case 0xF5:
if (valxor & 0x18) fdc_update_drvrate(1, (val & 0x18) >> 3);
break;
case 0xF6:
if (valxor & 0x18) fdc_update_drvrate(2, (val & 0x18) >> 3);
break;
case 0xF7:
if (valxor & 0x18) fdc_update_drvrate(3, (val & 0x18) >> 3);
break;
}
break;
case 3:
/* Parallel port */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
if (valxor)
{
fdc37c93x_lpt_handler();
}
break;
}
break;
case 4:
/* Serial port 1 */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
{
fdc37c93x_serial_handler(1);
}
break;
}
break;
case 5:
/* Serial port 2 */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
{
fdc37c93x_serial_handler(2);
}
break;
}
break;
case 8:
/* Serial port 2 */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
{
fdc37c93x_auxio_handler();
}
break;
}
break;
case 9:
/* Access bus (FDC37C932FR only) */
switch(fdc37c93x_curreg)
{
case 0x30:
case 0x60:
case 0x61:
case 0x70:
if (valxor)
{
fdc37c932fr_access_bus_handler();
}
break;
}
break;
}
}
static uint8_t fdc37c93x_read(uint16_t port, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
if (!fdc37c93x_locked)
{
return 0xff;
}
if (index)
return fdc37c93x_curreg;
else
{
if (fdc37c93x_curreg < 0x30)
{
return fdc37c93x_regs[fdc37c93x_curreg];
}
else
{
if ((fdc37c93x_regs[7] == 0) && (fdc37c93x_curreg == 0xF2)) return (fdc_get_rwc(0) | (fdc_get_rwc(1) << 2));
return fdc37c93x_ld_regs[fdc37c93x_regs[7]][fdc37c93x_curreg];
}
}
}
static void fdc37c93x_reset(void)
{
int i = 0;
memset(fdc37c93x_regs, 0, 48);
fdc37c93x_regs[3] = 3;
fdc37c93x_regs[0x21] = 1;
fdc37c93x_regs[0x24] = 4;
fdc37c93x_regs[0x26] = 0xF0;
fdc37c93x_regs[0x27] = 3;
for (i = 0; i < 10; i++)
{
memset(fdc37c93x_ld_regs[i], 0, 256);
}
/* Logical device 0: FDD */
fdc37c93x_ld_regs[0][0x30] = 1;
fdc37c93x_ld_regs[0][0x60] = 3;
fdc37c93x_ld_regs[0][0x61] = 0xF0;
fdc37c93x_ld_regs[0][0x70] = 6;
fdc37c93x_ld_regs[0][0x74] = 2;
fdc37c93x_ld_regs[0][0xF0] = 0xE;
fdc37c93x_ld_regs[0][0xF2] = 0xFF;
/* Logical device 1: IDE1 */
fdc37c93x_ld_regs[1][0x30] = 0;
fdc37c93x_ld_regs[1][0x60] = 1;
fdc37c93x_ld_regs[1][0x61] = 0xF0;
fdc37c93x_ld_regs[1][0x62] = 3;
fdc37c93x_ld_regs[1][0x63] = 0xF6;
fdc37c93x_ld_regs[1][0x70] = 0xE;
fdc37c93x_ld_regs[1][0xF0] = 0xC;
/* Logical device 2: IDE2 */
fdc37c93x_ld_regs[2][0x30] = 0;
fdc37c93x_ld_regs[2][0x60] = 1;
fdc37c93x_ld_regs[2][0x61] = 0x70;
fdc37c93x_ld_regs[2][0x62] = 3;
fdc37c93x_ld_regs[2][0x63] = 0x76;
fdc37c93x_ld_regs[2][0x70] = 0xF;
/* Logical device 3: Parallel Port */
fdc37c93x_ld_regs[3][0x30] = 1;
fdc37c93x_ld_regs[3][0x60] = 3;
fdc37c93x_ld_regs[3][0x61] = 0x78;
fdc37c93x_ld_regs[3][0x70] = 7;
fdc37c93x_ld_regs[3][0x74] = 4;
fdc37c93x_ld_regs[3][0xF0] = 0x3C;
/* Logical device 4: Serial Port 1 */
fdc37c93x_ld_regs[4][0x30] = 1;
fdc37c93x_ld_regs[4][0x60] = 3;
fdc37c93x_ld_regs[4][0x61] = 0xf8;
fdc37c93x_ld_regs[4][0x70] = 4;
fdc37c93x_ld_regs[4][0xF0] = 3;
serial_setup(1, 0x3f8, fdc37c93x_ld_regs[4][0x70]);
/* Logical device 5: Serial Port 2 */
fdc37c93x_ld_regs[5][0x30] = 1;
fdc37c93x_ld_regs[5][0x60] = 2;
fdc37c93x_ld_regs[5][0x61] = 0xf8;
fdc37c93x_ld_regs[5][0x70] = 3;
fdc37c93x_ld_regs[5][0x74] = 4;
fdc37c93x_ld_regs[5][0xF1] = 2;
fdc37c93x_ld_regs[5][0xF2] = 3;
serial_setup(2, 0x2f8, fdc37c93x_ld_regs[5][0x70]);
/* Logical device 6: RTC */
fdc37c93x_ld_regs[6][0x63] = 0x70;
fdc37c93x_ld_regs[6][0xF4] = 3;
/* Logical device 7: Keyboard */
fdc37c93x_ld_regs[7][0x30] = 1;
fdc37c93x_ld_regs[7][0x61] = 0x60;
fdc37c93x_ld_regs[7][0x70] = 1;
/* Logical device 8: Auxiliary I/O */
fdc37c93x_ld_regs[8][0x30] = 1;
fdc37c93x_ld_regs[8][0x61] = 0xEA;
/* Logical device 8: AUX I/O */
/* Logical device 9: ACCESS.bus */
fdc_update_densel_force(0);
fdd_swap = 0;
fdc_update_rwc(0, 0);
fdc_update_rwc(1, 0);
fdc_update_rwc(2, 0);
fdc_update_rwc(3, 0);
fdc_update_drvrate(0, 0);
fdc_update_drvrate(1, 0);
fdc_update_drvrate(2, 0);
fdc_update_drvrate(3, 0);
fdc_update_max_track(79);
io_removehandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
fdc37c93x_gpio_base = 0x00EA;
io_sethandler(fdc37c93x_gpio_base, 0x0001, fdc37c93x_gpio_read, NULL, NULL, fdc37c93x_gpio_write, NULL, NULL, NULL);
fdc37c93x_locked = 0;
}
static void fdc37c932fr_reset(void)
{
fdc37c93x_reset();
fdc37c93x_regs[0x20] = 3;
}
static void fdc37c935_reset(void)
{
fdc37c93x_reset();
fdc37c93x_regs[0x20] = 2;
}
static void fdc37c93x_init(void)
{
lpt2_remove();
fdc_remove();
fdc_add_for_superio();
fdc37c93x_gpio_reg = 0xFD;
io_sethandler(0x3f0, 0x0002, fdc37c93x_read, NULL, NULL, fdc37c93x_write, NULL, NULL, NULL);
}
void fdc37c932fr_init(void)
{
fdc37c93x_init();
fdc37c932fr_reset();
pci_reset_handler.super_io_reset = fdc37c932fr_reset;
}
void fdc37c935_init(void)
{
fdc37c93x_init();
fdc37c935_reset();
pci_reset_handler.super_io_reset = fdc37c935_reset;
}

9
src/win/Makefile.mingw
View File

@@ -8,7 +8,7 @@
#
# Makefile for Win32 (MinGW32) environment.
#
# Version: @(#)Makefile.mingw 1.0.66 2017/10/22
# Version: @(#)Makefile.mingw 1.0.68 2017/10/26
#
# Authors: Miran Grca, <mgrca8@gmail.com>
# Fred N. van Kempen, <decwiz@yahoo.com>
@@ -291,8 +291,11 @@ MCHOBJ := machine.o \
DEVOBJ := bugger.o lpt.o $(SERIAL) \
tandy_eeprom.o tandy_rom.o \
sio_detect.o \
sio_fdc37c665.o sio_fdc37c669.o sio_fdc37c932fr.o \
sio_pc87306.o sio_w83877f.o sio_um8669f.o piix.o \
sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \
sio_pc87306.o sio_w83877f.o \
sio_um8669f.o \
piix.o \
keyboard.o \
keyboard_xt.o keyboard_at.o keyboard_pcjr.o \
keyboard_amstrad.o keyboard_olim24.o \