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Minor changes on the ALi's & few other chipsets.

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This commit is contained in:
Panagiotis
2021-01-13 16:13:07 +02:00
committed by GitHub
parent e49a8231c9
commit 9ed2456ebb
4 changed files with 15 additions and 5 deletions
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5
src/chipset/ali1217.c
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@@ -62,6 +62,11 @@ static void ali1217_shadow_recalc(ali1217_t *dev)
mem_set_mem_state_both(0xc0000 + (i << 15), 0x8000, ((dev->regs[0x14] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xc0000 + (i << 15), 0x8000, ((dev->regs[0x14] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x14] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, ((dev->regs[0x15] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x15] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xe0000 + (i << 15), 0x8000, ((dev->regs[0x15] & (1 << (i * 2))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x15] & (1 << ((i * 2) + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
} }
shadowbios = !!(dev->regs[0x15] & 5);
shadowbios_write = !!(dev->regs[0x15] & 0x0a);
flushmmucache();
} }
static void static void

5
src/chipset/ali1531.c
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@@ -48,6 +48,11 @@ void ali1531_shadow_recalc(ali1531_t *dev)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4c] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4e] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY)); mem_set_mem_state_both(0xe0000 + (i << 14), 0x4000, (((dev->pci_conf[0x4d] >> i) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | (((dev->pci_conf[0x4f] >> i) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
} }
shadowbios = !!(dev->pci_conf[0x4d] & 0xf0);
shadowbios_write = !!(dev->pci_conf[0x4f] & 0xf0);
flushmmucache();
} }
void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev) void ali1531_smm_recalc(uint8_t smm_state, ali1531_t *dev)

4
src/chipset/intel_82335.c
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@@ -104,8 +104,8 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
if (!EXTENDED_GRANULARITY_ENABLED) if (!EXTENDED_GRANULARITY_ENABLED)
{ {
shadowbios = (dev->regs[0x22] & 0x01); shadowbios = !!(dev->regs[0x22] & 0x01);
shadowbios_write = (dev->regs[0x22] & 0x01); shadowbios_write = !!(dev->regs[0x22] & 0x01);
/* Base System 512/640KB set */ /* Base System 512/640KB set */
mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB); mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);

6
src/chipset/sis_5571.c
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@@ -88,8 +88,8 @@ sis_5571_shadow_recalc(sis_5571_t *dev)
can_read = (dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY; can_read = (dev->pci_conf[0x76] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
can_write = (dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY; can_write = (dev->pci_conf[0x76] & 0x20) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
shadowbios = (dev->pci_conf[0x76] & 0x80); shadowbios = !!(dev->pci_conf[0x76] & 0x80);
shadowbios_write = (dev->pci_conf[0x76] & 0x20); shadowbios_write = !!(dev->pci_conf[0x76] & 0x20);
mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write); mem_set_mem_state_both(0xf0000, 0x10000, can_read | can_write);
flushmmucache(); flushmmucache();
@@ -212,7 +212,7 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
case 0x51: /* Cache */ case 0x51: /* Cache */
dev->pci_conf[addr] = val; dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0x40); cpu_cache_ext_enabled = !!(val & 0x40);
cpu_update_waitstates(); cpu_update_waitstates();
break; break;