DDC: Clarify some comments
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@@ -138,12 +138,12 @@ ddc_init(void *i2c)
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memset(&edid->magic[1], 0xff, sizeof(edid->magic) - 2);
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edid->mfg[0] = 0x09; /* manufacturer "BOX" (apparently unassigned by UEFI) */
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edid->mfg[0] = 0x09; /* manufacturer "BOX" (currently unassigned by UEFI) */
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edid->mfg[1] = 0xf8;
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edid->mfg_week = 48;
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edid->mfg_year = 2020 - 1990;
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edid->edid_version = 0x01;
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edid->edid_rev = 0x04; /* EDID 1.4, required for Xorg on Linux to use the preferred mode timing */
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edid->edid_rev = 0x04; /* EDID 1.4, required for Xorg on newer Linux to use the preferred mode timing instead of maxing out */
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edid->input_params = 0x0e; /* analog input; separate sync; composite sync; sync on green */
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edid->horiz_size = round(horiz_mm / 10.0);
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@@ -207,7 +207,7 @@ ddc_init(void *i2c)
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/* Detailed timing for 1366x768 */
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DETAILED_TIMING(ext_detailed_timings[0], 85500, 1366, 768, 426, 30, 70, 143, 3, 3);
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/* High refresh rate timings (VGA is limited to 85 Hz) */
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/* High refresh rate timings (within the standard 85 Hz VGA limit) */
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edid->ext_descriptors[1].tag = 0xfa; /* standard timing identifiers */
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#define ext_standard_timings0 ext_descriptors[1].ext_standard_timings.timings
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STANDARD_TIMING(ext_standard_timings0[0], 640, STD_ASPECT_4_3, 85); /* 640x480 @ 85 Hz */
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