80486DX2-66/86Box-fork
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Even more fixes - the 6ABX3 now is fully implemented and works, except for the Super I/O chip.

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OBattler
2020-03-01 00:35:18 +01:00
parent d26dfc8f0e
commit a9ffc5b8c9
2 changed files with 7 additions and 7 deletions
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2
src/chipset/intel_4x0.c
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@@ -1189,7 +1189,7 @@ static void
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x90 : 0x92; regs[0x03] = 0x12; /* 82443BX */
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */
regs[0x08] = 0x02;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;

12
src/machine/m_at_socket8.c
View File

@@ -108,7 +108,7 @@ machine_at_6abx3_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/6axb3/6abx3h1.bin",
ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
@@ -118,12 +118,12 @@ machine_at_6abx3_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);