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@@ -710,10 +710,6 @@ static void sb_ess_write_reg(sb_dsp_t *dsp, uint8_t reg, uint8_t data)
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else
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dsp->sb_freq = 397700UL / (128ul - data);
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if (dsp->sb_16_enable || dsp->sb_8_enable) {
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sb_stop_dma_ess(dsp);
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sb_start_dma_ess(dsp);
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}
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break;
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}
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case 0xA2: /* Filter divider (effectively, a hardware lowpass filter under S/W control) */
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@@ -742,8 +738,15 @@ static void sb_ess_write_reg(sb_dsp_t *dsp, uint8_t reg, uint8_t data)
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ESSreg(reg) = data;
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if (chg & 0x3) {
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if (dsp->sb_16_enable || dsp->sb_8_enable) {
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sb_stop_dma_ess(dsp);
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sb_start_dma_ess(dsp);
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uint8_t real_format = 0x00;
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real_format |= !!(ESSreg(0xB7) & 0x20) ? 0x10 : 0;
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real_format |= !!(ESSreg(0xB7) & 0x8) ? 0x20 : 0;
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if (dsp->sb_16_enable)
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dsp->sb_16_format = real_format;
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if (dsp->sb_8_enable)
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dsp->sb_8_format = real_format;
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}
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}
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break;
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