Merge pull request #4119 from lemondrops/feature/cpuid_and_msr
CPUID and MSR fixes and improvements
This commit is contained in:
Miran Grča
GitHub
@@ -128,9 +128,9 @@ uint32_t addr64a_2[8];
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static pc_timer_t *cpu_fast_off_timer = NULL;
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static double cpu_fast_off_period = 0.0;
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#define AMD_SYSCALL_EIP (msr.star & 0xFFFFFFFF)
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#define AMD_SYSCALL_SB ((msr.star >> 32) & 0xFFFF)
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#define AMD_SYSRET_SB ((msr.star >> 48) & 0xFFFF)
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#define AMD_SYSCALL_EIP (msr.amd_star & 0xFFFFFFFF)
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#define AMD_SYSCALL_SB ((msr.amd_star >> 32) & 0xFFFF)
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#define AMD_SYSRET_SB ((msr.amd_star >> 48) & 0xFFFF)
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/* These #define's and enum have been borrowed from Bochs. */
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/* SMM feature masks */
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1400
src/cpu/cpu.c
1400
src/cpu/cpu.c
File diff suppressed because it is too large
Load Diff
149
src/cpu/cpu.h
149
src/cpu/cpu.h
@@ -226,101 +226,97 @@ typedef union {
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} MMX_REG;
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typedef struct {
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/* IDT WinChip and WinChip 2 MSR's */
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uint32_t tr1; /* 0x00000002, 0x0000000e */
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uint32_t tr12; /* 0x00000002, 0x0000000e */
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uint32_t cesr; /* 0x00000011 */
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/* IBM 386SLC/486SLC/486BL MSRs */
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uint64_t ibm_por; /* 0x00001000 - 386SLC and later */
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uint64_t ibm_crcr; /* 0x00001001 - 386SLC and later */
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uint64_t ibm_por2; /* 0x00001002 - 486SLC and later */
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uint64_t ibm_pcr; /* 0x00001004 - 486BL3 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
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/* IDT WinChip C6/2/VIA Cyrix III MSRs */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t mcr[8]; /* 0x00000110 - 0x00000117 (IDT) */
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uint32_t mcr_ctrl; /* 0x00000120 (IDT) */
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/* Weird long MSR's used by the Hyper-V BIOS. */
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uint64_t ecx20; /* 0x00000020, really 0x40000020, but we filter out the top 18 bits
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like a real Deschutes does. */
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/* AMD K5/K6 MSRs */
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uint64_t amd_aar; /* 0x00000082 - all K5 */
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uint64_t amd_hwcr; /* 0x00000083 - all K5 and all K6 */
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uint64_t amd_watmcr; /* 0x00000085 - K5 Model 1 and later */
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uint64_t amd_wapmrr; /* 0x00000086 - K5 Model 1 and later */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx79; /* 0x00000079 */
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uint64_t amd_efer; /* 0xc0000080 - all K5 and all K6 */
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uint64_t amd_star; /* 0xc0000081 - K6-2 and later */
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uint64_t amd_whcr; /* 0xc0000082 - all K5 and all K6 */
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uint64_t amd_uwccr; /* 0xc0000085 - K6-2C and later */
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uint64_t amd_epmr; /* 0xc0000086 - K6-III+/2+ only */
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uint64_t amd_psor; /* 0xc0000087 - K6-2C and later */
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uint64_t amd_pfir; /* 0xc0000088 - K6-2C and later */
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uint64_t amd_l2aar; /* 0xc0000089 - K6-III and later */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t ecx83; /* 0x00000083 - AMD K5 and K6 MSR's. */
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/* Pentium/Pentium MMX MSRs */
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uint64_t mcar; /* 0x00000000 - also on K5 and (R/W) K6 */
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uint64_t mctr; /* 0x00000001 - also on K5 and (R/W) K6 */
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uint32_t tr1; /* 0x00000002 - also on WinChip C6/2 */
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uint32_t tr2; /* 0x00000004 - reserved on PMMX */
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uint32_t tr3; /* 0x00000005 */
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uint32_t tr4; /* 0x00000006 */
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uint32_t tr5; /* 0x00000007 */
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uint32_t tr6; /* 0x00000008 */
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uint32_t tr7; /* 0x00000009 */
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uint32_t tr9; /* 0x0000000b */
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uint32_t tr10; /* 0x0000000c */
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uint32_t tr11; /* 0x0000000d */
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uint32_t tr12; /* 0x0000000e - also on WinChip C6/2 and K6 */
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uint32_t cesr; /* 0x00000011 - also on WinChip C6/2 and Cx6x86MX */
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uint64_t pmc[2]; /* 0x00000012, 0x00000013 - also on WinChip C6/2 and Cx6x86MX */
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uint32_t fp_last_xcpt; /* 0x8000001b - undocumented */
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uint32_t probe_ctl; /* 0x8000001d - undocumented */
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uint32_t ecx8000001e; /* 0x8000001e - undocumented */
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uint32_t ecx8000001f; /* 0x8000001f - undocumented */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx8x[4]; /* 0x00000088 - 0x0000008b */
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uint64_t ia32_pmc[8]; /* 0x000000c1 - 0x000000c8 */
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uint64_t mtrr_cap; /* 0x000000fe */
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/* Pentium Pro/II MSRs */
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uint64_t apic_base; /* 0x0000001b */
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uint32_t test_ctl; /* 0x00000033 */
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uint64_t bios_updt; /* 0x00000079 */
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/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
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uint64_t bbl_cr_dx[4]; /* 0x00000088 - 0x0000008b */
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uint64_t perfctr[2]; /* 0x000000c1, 0x000000c2 */
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uint64_t mtrr_cap; /* 0x000000fe */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t ecx116; /* 0x00000116 */
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uint64_t ecx11x[4]; /* 0x00000118 - 0x0000011b */
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uint64_t ecx11e; /* 0x0000011e */
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uint64_t bbl_cr_addr; /* 0x00000116 */
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uint64_t bbl_cr_decc; /* 0x00000118 */
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uint64_t bbl_cr_ctl; /* 0x00000119 */
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uint64_t bbl_cr_trig; /* 0x0000011a */
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uint64_t bbl_cr_busy; /* 0x0000011b */
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uint64_t bbl_cr_ctl3; /* 0x0000011e */
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/* Pentium II Klamath and Pentium II Deschutes MSR's */
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uint16_t sysenter_cs; /* 0x00000174 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_esp; /* 0x00000175 - SYSENTER/SYSEXIT MSR's */
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uint32_t sysenter_eip; /* 0x00000176 - SYSENTER/SYSEXIT MSR's */
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uint16_t sysenter_cs; /* 0x00000174 - Pentium II and later */
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uint32_t sysenter_esp; /* 0x00000175 - Pentium II and later */
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uint32_t sysenter_eip; /* 0x00000176 - Pentium II and later */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
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uint64_t ecx186; /* 0x00000186, 0x00000187 */
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uint64_t ecx187; /* 0x00000186, 0x00000187 */
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uint64_t mcg_ctl; /* 0x0000017b */
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uint64_t evntsel[2]; /* 0x00000186, 0x00000187 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t debug_ctl; /* 0x000001d9 - Debug Registers Control */
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uint64_t ecx1e0; /* 0x000001e0 */
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uint32_t debug_ctl; /* 0x000001d9 */
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uint32_t rob_cr_bkuptmpdr6; /* 0x000001e0 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f */
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/* MTTR-related MSRs also present on the VIA Cyrix III */
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uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f (ECX & 0) */
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uint64_t mtrr_physmask[8]; /* 0x00000200 - 0x0000020f (ECX & 1) */
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uint64_t mtrr_fix64k_8000; /* 0x00000250 */
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uint64_t mtrr_fix16k_8000; /* 0x00000258 */
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uint64_t mtrr_fix16k_a000; /* 0x00000259 */
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uint64_t mtrr_fix4k[8]; /* 0x00000268 - 0x0000026f */
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uint64_t mtrr_deftype; /* 0x000002ff */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t pat; /* 0x00000277 */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
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on the VIA Cyrix III */
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uint64_t mtrr_deftype; /* 0x000002ff */
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/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
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uint64_t mca_ctl[5]; /* 0x00000400, 0x00000404, 0x00000408, 0x0000040c, 0x00000410 - Machine Check Architecture */
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uint64_t pat; /* 0x00000277 - Pentium II Deschutes and later */
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uint64_t mca_ctl[5]; /* 0x00000400, 0x00000404, 0x00000408, 0x0000040c, 0x00000410 */
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uint64_t ecx570; /* 0x00000570 */
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/* IBM 386SLC, 486SLC, and 486BL MSR's */
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uint64_t ibm_por; /* 0x00001000 - Processor Operation Register */
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uint64_t ibm_crcr; /* 0x00001001 - Cache Region Control Register */
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/* IBM 486SLC and 486BL MSR's */
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uint64_t ibm_por2; /* 0x00001002 - Processor Operation Register */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_efer; /* 0xc0000080 */
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/* AMD K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t star; /* 0xc0000081 */
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/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_whcr; /* 0xc0000082 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_uwccr; /* 0xc0000085 */
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/* AMD K6-2P and K6-3P MSR's */
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uint64_t amd_epmr; /* 0xc0000086 */
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/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
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uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */
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/* K6-3, K6-2P, and K6-3P MSR's */
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uint64_t amd_l2aar; /* 0xc0000089 */
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/* Other/Unclassified MSRs */
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uint64_t ecx20; /* 0x00000020, really 0x40000020, but we filter out the top 18 bits
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like a real Deschutes does. */
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} msr_t;
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typedef struct {
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@@ -586,7 +582,6 @@ extern double bus_timing;
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extern double isa_timing;
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extern double pci_timing;
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extern double agp_timing;
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extern uint64_t pmc[2];
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extern uint16_t temp_seg_data[4];
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extern uint16_t cs_msr;
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extern uint32_t esp_msr;
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@@ -1398,9 +1398,9 @@ const cpu_family_t cpu_families[] = {
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.name = "Am5x86",
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.internal_name = "am5x86",
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.cpus = (const CPU[]) {
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{"P75", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
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{"P75+", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
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{"P90", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
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{"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
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{"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
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{"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
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{"", 0}
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}
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}, {
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@@ -1615,23 +1615,7 @@ const cpu_family_t cpu_families[] = {
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{
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.package = CPU_PKG_SOCKET5_7,
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.manufacturer = "AMD",
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.name = "K5 (5k86)",
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.internal_name = "k5_5k86",
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.cpus = (const CPU[]) {
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{"75 (P75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
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{"90 (P90)", CPU_K5, fpus_internal, 90000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2},
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{"100 (P100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
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{"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
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{"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
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{"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
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{"116.5 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
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{"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
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{"", 0}
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}
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}, {
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.package = CPU_PKG_SOCKET5_7,
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.manufacturer = "AMD",
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.name = "K5 (SSA/5)",
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.name = "K5 (Model 0)",
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.internal_name = "k5_ssa5",
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.cpus = (const CPU[]) {
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{"75 (PR75)", CPU_K5, fpus_internal, 75000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9},
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@@ -1639,6 +1623,19 @@ const cpu_family_t cpu_families[] = {
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{"100 (PR100)", CPU_K5, fpus_internal, 100000000, 1.5, 3520, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12},
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{"", 0}
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}
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}, {
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.package = CPU_PKG_SOCKET5_7,
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.manufacturer = "AMD",
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.name = "K5 (Model 1/2/3)",
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.internal_name = "k5_5k86",
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.cpus = (const CPU[]) {
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{"90 (PR120)", CPU_5K86, fpus_internal, 120000000, 2.0, 3520, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14},
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{"100 (PR133)", CPU_5K86, fpus_internal, 133333333, 2.0, 3520, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16},
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{"105 (PR150)", CPU_5K86, fpus_internal, 150000000, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2},
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{"116.7 (PR166)", CPU_5K86, fpus_internal, 166666666, 2.5, 3520, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20},
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{"133 (PR200)", CPU_5K86, fpus_internal, 200000000, 3.0, 3520, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24},
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{"", 0}
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}
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},
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#endif
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{
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@@ -1774,12 +1771,12 @@ const cpu_family_t cpu_families[] = {
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.name = "Cx6x86",
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.internal_name = "cx6x86",
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.cpus = (const CPU[]) {
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{"P90", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
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{"PR120+", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
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{"PR133+", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
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{"PR150+", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
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{"PR166+", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
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{"PR200+", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
|
||||
{"80 (PR90+)", CPU_Cx6x86, fpus_internal, 80000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10},
|
||||
{"100 (PR120+)", CPU_Cx6x86, fpus_internal, 100000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
|
||||
{"110 (PR133+)", CPU_Cx6x86, fpus_internal, 110000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
|
||||
{"120 (PR150+)", CPU_Cx6x86, fpus_internal, 120000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
|
||||
{"133 (PR166+)", CPU_Cx6x86, fpus_internal, 133333333, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"150 (PR200+)", CPU_Cx6x86, fpus_internal, 150000000, 2.0, 3520, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
|
||||
{"", 0}
|
||||
}
|
||||
}, {
|
||||
@@ -1788,10 +1785,10 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "Cx6x86L",
|
||||
.internal_name = "cx6x86l",
|
||||
.cpus = (const CPU[]) {
|
||||
{"PR133+", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
|
||||
{"PR150+", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
|
||||
{"PR166+", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"PR200+", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
|
||||
{"110 (PR133+)", CPU_Cx6x86L, fpus_internal, 110000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14},
|
||||
{"120 (PR150+)", CPU_Cx6x86L, fpus_internal, 120000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14},
|
||||
{"133 (PR166+)", CPU_Cx6x86L, fpus_internal, 133333333, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"150 (PR200+)", CPU_Cx6x86L, fpus_internal, 150000000, 2.0, 2800, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18},
|
||||
{"", 0}
|
||||
}
|
||||
}, {
|
||||
@@ -1800,10 +1797,10 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "Cx6x86MX",
|
||||
.internal_name = "cx6x86mx",
|
||||
.cpus = (const CPU[]) {
|
||||
{"PR166", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"PR200", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
|
||||
{"PR233", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
|
||||
{"PR266", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
|
||||
{"133 (PR166)", CPU_Cx6x86MX, fpus_internal, 133333333, 2.0, 2900, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16},
|
||||
{"166 (PR200)", CPU_Cx6x86MX, fpus_internal, 166666666, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20},
|
||||
{"187.5 (PR233)", CPU_Cx6x86MX, fpus_internal, 187500000, 2.5, 2900, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2},
|
||||
{"208.3 (PR266)", CPU_Cx6x86MX, fpus_internal, 208333333, 2.5, 2700, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25},
|
||||
{"", 0}
|
||||
}
|
||||
}, {
|
||||
@@ -1812,11 +1809,11 @@ const cpu_family_t cpu_families[] = {
|
||||
.name = "MII",
|
||||
.internal_name = "mii",
|
||||
.cpus = (const CPU[]) {
|
||||
{"PR300", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
|
||||
{"PR333", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
|
||||
{"PR366", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
|
||||
{"PR400", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34},
|
||||
{"PR433", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36},
|
||||
{"233 (PR300)", CPU_Cx6x86MX, fpus_internal, 233333333, 3.5, 2900, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28},
|
||||
{"250/83 (PR333)", CPU_Cx6x86MX, fpus_internal, 250000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30},
|
||||
{"250/100 (PR366)", CPU_Cx6x86MX, fpus_internal, 250000000, 2.5, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30},
|
||||
{"285 (PR400)", CPU_Cx6x86MX, fpus_internal, 285000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34},
|
||||
{"300 (PR433)", CPU_Cx6x86MX, fpus_internal, 300000000, 3.0, 2900, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36},
|
||||
{"", 0}
|
||||
}
|
||||
},
|
||||
|
||||
@@ -1,22 +0,0 @@
|
||||
/*
|
||||
* 86Box A hypervisor and IBM PC system emulator that specializes in
|
||||
* running old operating systems and software designed for IBM
|
||||
* PC systems and compatibles from 1981 through fairly recent
|
||||
* system designs based on the PCI bus.
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* x86 CPU segment emulation for the 286/386 interpreter.
|
||||
*
|
||||
*
|
||||
*
|
||||
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
|
||||
* Miran Grca, <mgrca8@gmail.com>
|
||||
*
|
||||
* Copyright 2008-2018 Sarah Walker.
|
||||
* Copyright 2016-2018 Miran Grca.
|
||||
*/
|
||||
#ifndef OPS_286_386
|
||||
# define OPS_286_386
|
||||
#endif
|
||||
#include "x86seg.c"
|
||||
Reference in New Issue
Block a user