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Tiny fix on the VIA PIPC suspension. Fixes dozens of boards.

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For some reason. SCI suspension was programmed while it's read-only.
This commit is contained in:
Panagiotis
2020-10-23 13:47:40 +03:00
committed by GitHub
parent 3465198d32
commit c9ee3864bf
1 changed files with 5 additions and 4 deletions
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9
src/chipset/via_pipc.c
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@@ -53,7 +53,7 @@
#include <86box/chipset.h>
#include <86box/sio.h>
#include <86box/hwm.h>
#define ENABLE_PIPC_LOG 1
/* Most revision numbers (PCI-ISA bridge or otherwise) were lifted from PCI device
listings on forums, as VIA's datasheets are not very helpful regarding those. */
@@ -268,8 +268,9 @@ pipc_reset_hard(void *priv)
dev->power_regs[0x08] = 0x40;
break;
}
if (dev->local >= VIA_PIPC_686A)
dev->power_regs[0x42] = 0x40; /* external suspend-related pin, must be set */
dev->power_regs[0x40] = 0x20;
dev->power_regs[0x42] = 0xd0;
dev->power_regs[0x48] = 0x01;
if (dev->local >= VIA_PIPC_686A)
@@ -754,7 +755,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x42:
dev->power_regs[addr] = val & 0x0f;
dev->power_regs[addr] = (dev->power_regs[0x42] & ~0x0f) | (val & 0x0f);
break;
case 0x61: case 0x62: case 0x63: