80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

Fixed SVGA VRAM limit checking; fixed CRTC 0x37 setting for the Vision 964.

Browse Source
This commit is contained in:
OBattler
2016-07-29 22:53:16 +02:00
parent 95ec4d5429
commit cd3fd7e726
2 changed files with 29 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/vid_s3.c
View File

@@ -922,7 +922,7 @@ uint8_t s3_in(uint16_t addr, void *p)
{
case 0x2d: return 0x88; /*Extended chip ID*/
case 0x2e:
if ((s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64)) return 0xFF;
// if ((s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64)) return 0xFF;
return s3->id_ext; /*New chip ID*/
case 0x2f: return 0; /*Revision level*/
case 0x30: return s3->id; /*Chip ID*/
@@ -2151,10 +2151,10 @@ static int vram_sizes[] =
7, /*512 kB*/
6, /*1 MB*/
4, /*2 MB*/
0,
2, /*3 MB*/
0, /*4 MB*/
0,
0,
5, /*6 MB*/
0,
3 /*8 MB*/
};
@@ -2194,6 +2194,7 @@ static void *s3_init(char *bios_fn, int chip)
else
svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4) | (vram_sizes[vram] << 5);
svga->crtc[0x37] = 1 | (7 << 5);
if (s3->chip == S3_VISION964) svga->crtc[0x37] |= 0xe;
s3_io_set(s3);
@@ -2495,10 +2496,18 @@ static device_config_t s3_miro_vision964_config[] =
.description = "2 MB",
.value = 2
},
{
.description = "3 MB",
.value = 3
},
{
.description = "4 MB",
.value = 4
},
{
.description = "6 MB",
.value = 6
},
{
.description = "8 MB",
.value = 8

33
src/vid_svga.c
View File

@@ -860,7 +860,7 @@ void svga_write(uint32_t addr, uint8_t val, void *p)
{
addr<<=2;
}
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return;
@@ -1027,13 +1027,14 @@ uint8_t svga_read(uint32_t addr, void *p)
addr &= svga->banked_mask;
addr += svga->read_bank;
latch_addr = (addr << 2) % svga->vram_limit;
// latch_addr = (addr << 2) % svga->vram_limit;
latch_addr = (addr << 2);
// pclog("%05X %i %04X:%04X %02X %02X %i\n",addr,svga->chain4,CS,pc, vram[addr & 0x7fffff], vram[(addr << 2) & 0x7fffff], svga->readmode);
// pclog("%i\n", svga->readmode);
if (svga->chain4 || svga->fb_only)
{
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return 0xff;
return svga->vram[addr];
@@ -1047,7 +1048,7 @@ uint8_t svga_read(uint32_t addr, void *p)
else
addr<<=2;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return 0xff;
@@ -1120,7 +1121,7 @@ void svga_write_linear(uint32_t addr, uint8_t val, void *p)
{
addr<<=2;
}
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return;
if (svga_output) pclog("%08X\n", addr);
@@ -1283,10 +1284,10 @@ uint8_t svga_read_linear(uint32_t addr, void *p)
if (svga->chain4 || svga->fb_only)
{
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return 0xff;
return svga->vram[addr % svga->vram_limit];
return svga->vram[addr];
}
else if (svga->chain2_read)
{
@@ -1297,7 +1298,7 @@ uint8_t svga_read_linear(uint32_t addr, void *p)
else
addr<<=2;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if (addr >= svga->vram_limit)
return 0xff;
@@ -1412,7 +1413,7 @@ void svga_writew(uint32_t addr, uint16_t val, void *p)
if (svga_output) pclog("svga_writew: %05X ", addr);
addr = (addr & svga->banked_mask) + svga->write_bank;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return;
if (addr >= svga->vram_limit)
return;
@@ -1443,7 +1444,7 @@ void svga_writel(uint32_t addr, uint32_t val, void *p)
if (svga_output) pclog("svga_writel: %05X ", addr);
addr = (addr & svga->banked_mask) + svga->write_bank;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return;
if (addr >= svga->vram_limit)
return;
@@ -1469,7 +1470,7 @@ uint16_t svga_readw(uint32_t addr, void *p)
// pclog("Readw %05X ", addr);
addr = (addr & svga->banked_mask) + svga->read_bank;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return 0xffff;
// pclog("%08X %04X\n", addr, *(uint16_t *)&vram[addr]);
if (addr >= svga->vram_limit) return 0xffff;
@@ -1493,7 +1494,7 @@ uint32_t svga_readl(uint32_t addr, void *p)
// pclog("Readl %05X ", addr);
addr = (addr & svga->banked_mask) + svga->read_bank;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return 0xffffffff;
// pclog("%08X %08X\n", addr, *(uint32_t *)&vram[addr]);
if (addr >= svga->vram_limit) return 0xffffffff;
@@ -1520,7 +1521,7 @@ void svga_writew_linear(uint32_t addr, uint16_t val, void *p)
cycles_lost += video_timing_w;
if (svga_output) pclog("Write LFBw %08X %04X\n", addr, val);
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return;
if (addr >= svga->vram_limit)
return;
@@ -1549,7 +1550,7 @@ void svga_writel_linear(uint32_t addr, uint32_t val, void *p)
cycles_lost += video_timing_l;
if (svga_output) pclog("Write LFBl %08X %08X\n", addr, val);
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return;
if (addr >= svga->vram_limit)
return;
@@ -1571,7 +1572,7 @@ uint16_t svga_readw_linear(uint32_t addr, void *p)
cycles -= video_timing_w;
cycles_lost += video_timing_w;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return 0xffff;
if (addr >= svga->vram_limit) return 0xffff;
@@ -1592,7 +1593,7 @@ uint32_t svga_readl_linear(uint32_t addr, void *p)
cycles -= video_timing_l;
cycles_lost += video_timing_l;
addr %= svga->vram_limit;
// addr %= svga->vram_limit;
if ((!svga->extvram) && (addr >= 0x10000)) return 0xffffffff;
if (addr >= svga->vram_limit) return 0xffffffff;