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Merge pull request #875 from richardg867/master

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DRB locking fixes
This commit is contained in:
Miran Grča
2020-06-27 03:24:15 +02:00
committed by GitHub
parent af9526b47d 9cecbfa33a
commit d3880e21ac
9 changed files with 92 additions and 90 deletions
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29
src/chipset/intel_420ex.c
View File

@@ -180,33 +180,6 @@ i420ex_smram_handler_phase1(i420ex_t *dev)
}
static void
i420ex_write_drbs(i420ex_t *dev)
{
uint8_t row, dimm;
uint16_t size, vslots[SPD_MAX_SLOTS];
/* No SPD: let the SPD code split SIMMs into pairs as if they were "DIMM"s. */
dimm = (4 + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(vslots, dimm, (mem_size >> 10), 1, 1 << (log2_ui16(machines[machine].max_ram / dimm)), 0);
/* Write DRBs for each row. */
i420ex_log("Writing DRBs...\n");
for (row = 0; row <= 4; row++) {
dimm = (row >> 1);
/* No SPD: use the values calculated above. */
size = (vslots[dimm] >> 1);
/* Populate DRB register, adding the previous DRB's value.. */
dev->regs[0x60 | row] = ((row > 0) ? dev->regs[0x60 | (row - 1)] : 0);
if (size)
dev->regs[0x60 | row] += size;
i420ex_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, dev->regs[0x60 | row]);
}
}
static void
i420ex_write(int func, int addr, uint8_t val, void *priv)
{
@@ -333,7 +306,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
dev->regs[0x5f] = val;
break;
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64:
i420ex_write_drbs(dev);
spd_write_drbs(dev->regs, 0x60, 0x64, 1);
break;
case 0x66: case 0x67:
i420ex_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x01), val);

50
src/chipset/intel_4x0.c
View File

@@ -29,7 +29,6 @@
#include <86box/keyboard.h>
#include <86box/chipset.h>
#include <86box/spd.h>
#include <86box/machine.h>
enum
@@ -269,47 +268,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
}
static void
i4x0_write_drbs(i4x0_t *dev)
{
uint8_t row, dimm;
uint16_t size, vslots[SPD_MAX_SLOTS];
/* No SPD: let the SPD code split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = (dev->max_drb + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(vslots, dimm, (mem_size >> 10), dev->drb_unit, 1 << (log2_ui16(machines[machine].max_ram / dimm)), 0);
}
/* Write DRBs for each row. */
i4x0_log("Writing DRBs... unit=%d max=%d\n", dev->drb_unit, dev->max_drb);
for (row = 0; row <= dev->max_drb; row++) {
dimm = (row >> 1);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_devices[dimm]) {
if (spd_devices[dimm]->row1 < dev->drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = ((row & 1) ? 0 : dev->drb_unit);
else
size = ((row & 1) ? spd_devices[dimm]->row2 : spd_devices[dimm]->row1);
}
} else {
/* No SPD: use the values calculated above. */
size = (vslots[dimm] >> 1);
}
/* Populate DRB register, adding the previous DRB's value.
This will intentionally overflow on 440GX with 2 GB. */
dev->regs[0][0x60 | row] = ((row > 0) ? dev->regs[0][0x60 | (row - 1)] : 0);
if (size)
dev->regs[0][0x60 | row] += (size / dev->drb_unit);
i4x0_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, dev->regs[0][0x60 | row]);
}
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
@@ -692,7 +650,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64:
if ((addr & 0x7) <= dev->max_drb) {
i4x0_write_drbs(dev);
spd_write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
@@ -715,7 +673,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x65:
if ((addr & 0x7) <= dev->max_drb) {
i4x0_write_drbs(dev);
spd_write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
@@ -738,7 +696,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x66:
if ((addr & 0x7) <= dev->max_drb) {
i4x0_write_drbs(dev);
spd_write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {
@@ -752,7 +710,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x67:
if ((addr & 0x7) <= dev->max_drb) {
i4x0_write_drbs(dev);
spd_write_drbs(regs, 0x60, 0x60 + dev->max_drb, dev->drb_unit);
break;
}
switch (dev->type) {

8
src/chipset/via_apollo.c
View File

@@ -32,6 +32,7 @@
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
#include <86box/spd.h>
typedef struct via_apollo_t
@@ -226,6 +227,13 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
dev->pci_conf[0][0x53] = (dev->pci_conf[0][0x53] & ~0xf0) | (val & 0xf0);
break;
case 0x56: case 0x57: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: /* DRAM Row Ending Address */
if (dev->id >= 0x0691)
spd_write_drbs(dev->pci_conf[0], 0x5a, 0x56, 8);
else if (addr >= 0x5a)
spd_write_drbs(dev->pci_conf[0], 0x5a, 0x5f, 8);
break;
case 0x58:
if (dev->id == 0x0597)
dev->pci_conf[0][0x58] = (dev->pci_conf[0][0x58] & ~0xee) | (val & 0xee);

6
src/chipset/via_vpx.c
View File

@@ -35,6 +35,7 @@
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
#include <86box/spd.h>
typedef struct via_vpx_t
{
@@ -94,6 +95,10 @@ via_vpx_t *dev = (via_vpx_t *) priv;
dev->pci_conf[0x07] &= ~(val & 0xb0);
break;
case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: // Bank Ending
spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, 4);
break;
case 0x61: // Shadow RAM control 1
if ((dev->pci_conf[0x61] ^ val) & 0x03)
vpx_map(0xc0000, 0x04000, val & 0x03);
@@ -201,6 +206,7 @@ via_vpx_init(const device_t *info)
dev->pci_conf[0x5e] = 1; // Bank 4 Ending
dev->pci_conf[0x5f] = 1; // Bank 5 Ending
dev->pci_conf[0x60] = 0x3f; // DRAM type
dev->pci_conf[0x64] = 0xab; // DRAM reference timing
return dev;

7
src/include/86box/spd.h
View File

@@ -100,13 +100,8 @@ typedef struct _spd_sdram_ {
} spd_sdram_t;
extern int spd_present;
extern spd_t *spd_devices[SPD_MAX_SLOTS];
extern uint8_t log2_ui16(uint16_t i);
extern void spd_populate(uint16_t *vslots, uint8_t slot_count, uint16_t total_size, uint16_t min_module_size, uint16_t max_module_size, uint8_t enable_asym);
extern void spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size);
extern void spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
#endif /*EMU_SPD_H*/

2
src/machine/m_at_socket7_s7.c
View File

@@ -983,6 +983,7 @@ machine_at_ficva502_init(const machine_t *model)
device_add(&keyboard_ps2_pci_device);
device_add(&fdc37c669_device);
device_add(&sst_flash_29ee010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
return ret;
}
@@ -1013,6 +1014,7 @@ machine_at_ficpa2012_init(const machine_t *model)
device_add(&keyboard_ps2_pci_device);
device_add(&w83877f_device);
device_add(&sst_flash_39sf010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}

5
src/machine/m_at_sockets7.c
View File

@@ -67,7 +67,7 @@ machine_at_ax59pro_init(const machine_t *model)
device_add(&keyboard_ps2_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_39sf020_device);
spd_register(SPD_TYPE_SDRAM, 0xF, 256);
spd_register(SPD_TYPE_SDRAM, 0x7, 512);
return ret;
}
@@ -90,7 +90,7 @@ machine_at_mvp3_init(const machine_t *model)
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0a, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device);
@@ -98,6 +98,7 @@ machine_at_mvp3_init(const machine_t *model)
device_add(&keyboard_ps2_pci_device);
device_add(&w83877tf_device);
device_add(&sst_flash_39sf010_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 512);
return ret;
}

10
src/machine/machine_table.c
View File

@@ -297,12 +297,12 @@ const machine_t machines[] = {
{ "[VIA VPX] FIC VA-502", "ficva502", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 127, machine_at_ficva502_init, NULL },
/* Apollo VP3 */
{ "[VIA VP3] FIC PA-2012", "ficpa2012", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 192, 8, 127, machine_at_ficpa2012_init, NULL },
{ "[VIA VP3] FIC PA-2012", "ficpa2012", MACHINE_TYPE_SOCKET7, MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_ficpa2012_init, NULL },
/* Super Socket 7 machines */
/* Apollo MVP3 */
{ "[VIA MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_ax59pro_init, NULL },
{ "[VIA MVP3] FIC VA-503+", "ficva503p", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_mvp3_init, NULL },
{ "[VIA MVP3] AOpen AX59 Pro", "ax59pro", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_ax59pro_init, NULL },
{ "[VIA MVP3] FIC VA-503+", "ficva503p", MACHINE_TYPE_SOCKETS7, MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_mvp3_init, NULL },
/* Socket 8 machines */
/* 440FX */
@@ -348,13 +348,13 @@ const machine_t machines[] = {
/* 440BX */
{ "[i440BX] ASUS CUBX", "cubx", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_cubx_init, NULL },
{ "[i440BX] A-Trend ATC7020BXII", "atc7020bxii", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_atc7020bxii_init, NULL },
{ "[i440BX] AmazePC AM-BX133", "ambx133", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ambx133_init, NULL },
{ "[i440BX] AmazePC AM-BX133", "ambx133", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_ambx133_init, NULL },
/* 440ZX */
{ "[i440ZX] Soltek SL-63A1", "63a", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_63a_init, NULL },
/* VIA Apollo Pro */
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_apas3_init, NULL },
{ "[VIA Apollo Pro] PC Partner APAS3", "apas3", MACHINE_TYPE_SOCKET370, {{"Intel", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_apas3_init, NULL },
{ NULL, NULL, MACHINE_TYPE_NONE, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
};

65
src/mem/spd.c
View File

@@ -26,6 +26,7 @@
#include <86box/smbus.h>
#include <86box/spd.h>
#include <86box/version.h>
#include <86box/machine.h>
#define MIN(a, b) ((a) < (b) ? (a) : (b))
@@ -118,6 +119,8 @@ spd_close(void *priv)
spd_write_byte, NULL, NULL, NULL,
dev);
spd_present = 0;
free(dev);
}
@@ -134,6 +137,8 @@ spd_init(const device_t *info)
spd_write_byte, NULL, NULL, NULL,
dev);
spd_present = 1;
return dev;
}
@@ -393,9 +398,63 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
break;
}
//device_add(info);
device_add(info);
vslot++;
}
spd_present = 1;
}
void
spd_write_drbs(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit)
{
uint8_t row, dimm, drb, apollo = 0;
uint16_t size, vslots[SPD_MAX_SLOTS];
/* Special case for VIA Apollo Pro family, which jumps from 5F to 56. */
if (reg_max < reg_min) {
apollo = reg_max;
reg_max = reg_min + 7;
}
/* No SPD: split SIMMs into pairs as if they were "DIMM"s. */
if (!spd_present) {
dimm = ((reg_max - reg_min) + 1) >> 1; /* amount of "DIMM"s, also used to determine the maximum "DIMM" size */
spd_populate(vslots, dimm, (mem_size >> 10), drb_unit, 1 << (log2_ui16(machines[machine].max_ram / dimm)), 0);
}
/* Write DRBs for each row. */
spd_log("Writing DRBs... regs=[%02X:%02X] unit=%d\n", reg_min, reg_max, drb_unit);
for (row = 0; row <= (reg_max - reg_min); row++) {
dimm = (row >> 1);
size = 0;
if (spd_present) {
/* SPD enabled: use SPD info for this slot, if present. */
if (spd_devices[dimm]) {
if (spd_devices[dimm]->row1 < drb_unit) /* hack within a hack: turn a double-sided DIMM that is too small into a single-sided one */
size = ((row & 1) ? 0 : drb_unit);
else
size = ((row & 1) ? spd_devices[dimm]->row2 : spd_devices[dimm]->row1);
}
} else {
/* No SPD: use the values calculated above. */
size = (vslots[dimm] >> 1);
}
/* Determine the DRB register to write. */
drb = reg_min + row;
if ((apollo) && ((drb & 0xf) < 0xa))
drb = apollo + (drb & 0xf);
/* Write DRB register, adding the previous DRB's value. */
if (row == 0)
regs[drb] = 0;
else if ((apollo) && (drb == apollo))
regs[drb] = regs[drb | 0xf]; /* 5F comes before 56 */
else
regs[drb] = regs[drb - 1];
if (size)
regs[drb] += (size / drb_unit); /* this will intentionally overflow on 440GX with 2 GB */
spd_log("DRB[%d] = %d MB (%02Xh raw)\n", row, size, regs[drb]);
}
}