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More ViRGE fixes (August 29th, 2024)

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Apparently the extended sequencer registers (>= 0x20) are required to have sane values on the STREAMS engine on GX2 and probably other chips in the ViRGE range.
This commit is contained in:
TC1995
2024-08-29 00:51:28 +02:00
parent 818c268f75
commit dd5c5f4a07
1 changed files with 4 additions and 5 deletions
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9
src/video/vid_s3_virge.c
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@@ -471,7 +471,8 @@ s3_virge_update_irqs(virge_t *virge) {
}
static void
s3_virge_out(uint16_t addr, uint8_t val, void *priv) {
s3_virge_out(uint16_t addr, uint8_t val, void *priv)
{
virge_t *virge = (virge_t *) priv;
svga_t * svga = &virge->svga;
uint8_t old;
@@ -483,7 +484,7 @@ s3_virge_out(uint16_t addr, uint8_t val, void *priv) {
switch (addr) {
case 0x3c5:
if (svga->seqaddr >= 0x10) {
svga->seqregs[svga->seqaddr & 0x1f] = val;
svga->seqregs[svga->seqaddr] = val;
svga_recalctimings(svga);
return;
}
@@ -519,8 +520,6 @@ s3_virge_out(uint16_t addr, uint8_t val, void *priv) {
return;
if ((svga->crtcreg == 0x36) && (svga->crtc[0x39] != 0xa5))
return;
if (svga->crtcreg >= 0x80)
return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
@@ -707,7 +706,7 @@ s3_virge_in(uint16_t addr, void *priv) {
case 0x3c5:
if (svga->seqaddr >= 8)
ret = svga->seqregs[svga->seqaddr & 0x1f];
ret = svga->seqregs[svga->seqaddr];
else if (svga->seqaddr <= 4)
ret = svga_in(addr, svga);
else