80486DX2-66/86Box-fork
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Applied the mainline PCem commit that reorganizes the REP instructions.

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This commit is contained in:
OBattler
2017-07-21 10:51:54 +02:00
parent 6cab132b30
commit dd93543bad
11 changed files with 1036 additions and 840 deletions
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822
src/CPU/386_dynarec.c
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@@ -401,828 +401,6 @@ int checkio(int port)
return d&(1<<(port&7));
}
int rep386(int fv)
{
uint8_t temp;
uint32_t c;
uint8_t temp2;
uint16_t tempw,tempw2,of;
uint32_t ipc = cpu_state.oldpc;
uint32_t rep32 = cpu_state.op32;
uint32_t templ,templ2;
int tempz;
int tempi;
/*Limit the amount of time the instruction is uninterruptable for, so
that high frequency timers still work okay. This amount is different
for interpreter and recompiler*/
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100);
int reads = 0, reads_l = 0, writes = 0, writes_l = 0, total_cycles = 0;
if (trap)
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
cpu_reps++;
flags_rebuild();
of = flags;
startrep:
temp=opcode2=readmemb(cs,cpu_state.pc); cpu_state.pc++;
c=(rep32&0x200)?ECX:CX;
switch (temp|rep32)
{
case 0xC3: case 0x1C3: case 0x2C3: case 0x3C3:
cpu_state.pc--;
break;
case 0x08:
cpu_state.pc=ipc+1;
break;
case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
cpu_state.ea_seg = &_es;
PREFETCH_PREFIX();
goto startrep;
break;
case 0x2E: case 0x12E: case 0x22E: case 0x32E: /*CS:*/
cpu_state.ea_seg = &_cs;
PREFETCH_PREFIX();
goto startrep;
case 0x36: case 0x136: case 0x236: case 0x336: /*SS:*/
cpu_state.ea_seg = &_ss;
PREFETCH_PREFIX();
goto startrep;
case 0x3E: case 0x13E: case 0x23E: case 0x33E: /*DS:*/
cpu_state.ea_seg = &_ds;
PREFETCH_PREFIX();
goto startrep;
case 0x64: case 0x164: case 0x264: case 0x364: /*FS:*/
cpu_state.ea_seg = &_fs;
PREFETCH_PREFIX();
goto startrep;
case 0x65: case 0x165: case 0x265: case 0x365: /*GS:*/
cpu_state.ea_seg = &_gs;
PREFETCH_PREFIX();
goto startrep;
case 0x66: case 0x166: case 0x266: case 0x366: /*Data size prefix*/
rep32 = (rep32 & 0x200) | ((use32 ^ 0x100) & 0x100);
PREFETCH_PREFIX();
goto startrep;
case 0x67: case 0x167: case 0x267: case 0x367: /*Address size prefix*/
rep32 = (rep32 & 0x100) | ((use32 ^ 0x200) & 0x200);
PREFETCH_PREFIX();
goto startrep;
case 0x6C: case 0x16C: /*REP INSB*/
if (c>0)
{
checkio_perm(DX);
temp2=inb(DX);
writememb(es,DI,temp2);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI--;
else DI++;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26C: case 0x36C: /*REP INSB*/
if (c>0)
{
checkio_perm(DX);
temp2=inb(DX);
writememb(es,EDI,temp2);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI--;
else EDI++;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6D: /*REP INSW*/
if (c>0)
{
tempw=inw(DX);
writememw(es,DI,tempw);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI-=2;
else DI+=2;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x16D: /*REP INSL*/
if (c>0)
{
templ=inl(DX);
writememl(es,DI,templ);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI-=4;
else DI+=4;
c--;
cycles-=15;
reads_l++; writes_l++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26D: /*REP INSW*/
if (c>0)
{
tempw=inw(DX);
writememw(es,EDI,tempw);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI-=2;
else EDI+=2;
c--;
cycles-=15;
reads++; writes++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x36D: /*REP INSL*/
if (c>0)
{
templ=inl(DX);
writememl(es,EDI,templ);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI-=4;
else EDI+=4;
c--;
cycles-=15;
reads_l++; writes_l++; total_cycles += 15;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6E: case 0x16E: /*REP OUTSB*/
if (c>0)
{
temp2 = readmemb(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
checkio_perm(DX);
outb(DX,temp2);
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x26E: case 0x36E: /*REP OUTSB*/
if (c>0)
{
temp2 = readmemb(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
checkio_perm(DX);
outb(DX,temp2);
if (flags&D_FLAG) ESI--;
else ESI++;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x6F: /*REP OUTSW*/
if (c>0)
{
tempw = readmemw(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
outw(DX,tempw);
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x16F: /*REP OUTSL*/
if (c > 0)
{
templ = readmeml(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
outl(DX, templ);
if (flags & D_FLAG) SI -= 4;
else SI += 4;
c--;
cycles -= 14;
reads_l++; writes_l++; total_cycles += 14;
}
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
break;
case 0x26F: /*REP OUTSW*/
if (c>0)
{
tempw = readmemw(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
outw(DX,tempw);
if (flags&D_FLAG) ESI-=2;
else ESI+=2;
c--;
cycles-=14;
reads++; writes++; total_cycles += 14;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x36F: /*REP OUTSL*/
if (c > 0)
{
templ = readmeml(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
outl(DX, templ);
if (flags & D_FLAG) ESI -= 4;
else ESI += 4;
c--;
cycles -= 14;
reads_l++; writes_l++; total_cycles += 14;
}
if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
else firstrepcycle = 1;
break;
case 0x90: case 0x190: /*REP NOP*/
case 0x290: case 0x390:
break;
case 0xA4: case 0x1A4: /*REP MOVSB*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI);
temp2 = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
writememb(es,DI,temp2); if (cpu_state.abrt) break;
if (flags&D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2A4: case 0x3A4: /*REP MOVSB*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI);
temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
writememb(es,EDI,temp2); if (cpu_state.abrt) break;
if (flags&D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xA5: /*REP MOVSW*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI+1);
tempw = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
writememw(es,DI,tempw); if (cpu_state.abrt) break;
if (flags&D_FLAG) { DI-=2; SI-=2; }
else { DI+=2; SI+=2; }
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1A5: /*REP MOVSL*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI+3);
templ = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
writememl(es,DI,templ); if (cpu_state.abrt) break;
if (flags&D_FLAG) { DI-=4; SI-=4; }
else { DI+=4; SI+=4; }
c--;
cycles-=(is486)?3:4;
ins++;
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2A5: /*REP MOVSW*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI+1);
tempw = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
writememw(es,EDI,tempw); if (cpu_state.abrt) break;
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
else { EDI+=2; ESI+=2; }
c--;
cycles-=(is486)?3:4;
ins++;
reads++; writes++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3A5: /*REP MOVSL*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI+3);
templ = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
writememl(es,EDI,templ); if (cpu_state.abrt) break;
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
else { EDI+=4; ESI+=4; }
c--;
cycles-=(is486)?3:4;
ins++;
reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xA6: case 0x1A6: /*REP CMPSB*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
temp = readmemb(cpu_state.ea_seg->base, SI);
temp2=readmemb(es,DI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2A6: case 0x3A6: /*REP CMPSB*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
temp = readmemb(cpu_state.ea_seg->base, ESI);
temp2=readmemb(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub8(temp,temp2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0xA7: /*REP CMPSW*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
tempw = readmemw(cpu_state.ea_seg->base, SI);
tempw2=readmemw(es,DI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { DI-=2; SI-=2; }
else { DI+=2; SI+=2; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x1A7: /*REP CMPSL*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
templ = readmeml(cpu_state.ea_seg->base, SI);
templ2=readmeml(es,DI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { DI-=4; SI-=4; }
else { DI+=4; SI+=4; }
c--;
cycles-=(is486)?7:9;
reads_l += 2; total_cycles += is486 ? 7 : 9;
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2A7: /*REP CMPSW*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
tempw = readmemw(cpu_state.ea_seg->base, ESI);
tempw2=readmemw(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
else { EDI+=2; ESI+=2; }
c--;
cycles-=(is486)?7:9;
reads += 2; total_cycles += is486 ? 7 : 9;
setsub16(tempw,tempw2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x3A7: /*REP CMPSL*/
tempz = (fv) ? 1 : 0;
if ((c>0) && (fv==tempz))
{
templ = readmeml(cpu_state.ea_seg->base, ESI);
templ2=readmeml(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
else { EDI+=4; ESI+=4; }
c--;
cycles-=(is486)?7:9;
reads_l += 2; total_cycles += is486 ? 7 : 9;
setsub32(templ,templ2);
tempz = (ZF_SET()) ? 1 : 0;
}
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0xAA: case 0x1AA: /*REP STOSB*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI);
writememb(es,DI,AL);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI--;
else DI++;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AA: case 0x3AA: /*REP STOSB*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI);
writememb(es,EDI,AL);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI--;
else EDI++;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAB: /*REP STOSW*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI+1);
writememw(es,DI,AX);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI-=2;
else DI+=2;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AB: /*REP STOSW*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI+1);
writememw(es,EDI,AX);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI-=2;
else EDI+=2;
c--;
cycles-=(is486)?4:5;
writes++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1AB: /*REP STOSL*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, DI, DI+3);
writememl(es,DI,EAX);
if (cpu_state.abrt) break;
if (flags&D_FLAG) DI-=4;
else DI+=4;
c--;
cycles-=(is486)?4:5;
writes_l++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3AB: /*REP STOSL*/
while (c > 0)
{
CHECK_WRITE_REP(&_es, EDI, EDI+3);
writememl(es,EDI,EAX);
if (cpu_state.abrt) break;
if (flags&D_FLAG) EDI-=4;
else EDI+=4;
c--;
cycles-=(is486)?4:5;
writes_l++; total_cycles += is486 ? 4 : 5;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAC: case 0x1AC: /*REP LODSB*/
if (c>0)
{
AL = readmemb(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) SI--;
else SI++;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AC: case 0x3AC: /*REP LODSB*/
if (c>0)
{
AL = readmemb(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) ESI--;
else ESI++;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAD: /*REP LODSW*/
if (c>0)
{
AX = readmemw(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) SI-=2;
else SI+=2;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x1AD: /*REP LODSL*/
if (c>0)
{
EAX = readmeml(cpu_state.ea_seg->base, SI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) SI-=4;
else SI+=4;
c--;
cycles-=5;
reads_l++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x2AD: /*REP LODSW*/
if (c>0)
{
AX = readmemw(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) ESI-=2;
else ESI+=2;
c--;
cycles-=5;
reads++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0x3AD: /*REP LODSL*/
if (c>0)
{
EAX = readmeml(cpu_state.ea_seg->base, ESI);
if (cpu_state.abrt) break;
if (flags&D_FLAG) ESI-=4;
else ESI+=4;
c--;
cycles-=5;
reads_l++; total_cycles += 5;
}
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
else firstrepcycle=1;
break;
case 0xAE: case 0x1AE: /*REP SCASB*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
temp2=readmemb(es,DI);
if (cpu_state.abrt) { flags=of; break; }
setsub8(AL,temp2);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) DI--;
else DI++;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2AE: case 0x3AE: /*REP SCASB*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
temp2=readmemb(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
setsub8(AL,temp2);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) EDI--;
else EDI++;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0xAF: /*REP SCASW*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
tempw=readmemw(es,DI);
if (cpu_state.abrt) { flags=of; break; }
setsub16(AX,tempw);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) DI-=2;
else DI+=2;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x1AF: /*REP SCASL*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
templ=readmeml(es,DI);
if (cpu_state.abrt) { flags=of; break; }
setsub32(EAX,templ);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) DI-=4;
else DI+=4;
c--;
cycles-=(is486)?5:8;
reads_l++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x2AF: /*REP SCASW*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
tempw=readmemw(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
setsub16(AX,tempw);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) EDI-=2;
else EDI+=2;
c--;
cycles-=(is486)?5:8;
reads++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
case 0x3AF: /*REP SCASL*/
cpu_notreps++;
tempz = (fv) ? 1 : 0;
while ((c > 0) && (fv == tempz))
{
templ=readmeml(es,EDI);
if (cpu_state.abrt) { flags=of; break; }
setsub32(EAX,templ);
tempz = (ZF_SET()) ? 1 : 0;
if (flags&D_FLAG) EDI-=4;
else EDI+=4;
c--;
cycles-=(is486)?5:8;
reads_l++; total_cycles += is486 ? 5 : 8;
ins++;
if (cycles < cycles_end)
break;
}
ins--;
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
else firstrepcycle=1;
break;
default:
cpu_state.pc = ipc+1;
break;
}
if (rep32&0x200) ECX=c;
else CX=c;
CPU_BLOCK_END();
PREFETCH_RUN(total_cycles, 1, -1, reads, reads_l, writes, writes_l, 0);
return cpu_state.abrt;
}
int xout=0;

182
src/CPU/386_ops.h
View File

@@ -1410,4 +1410,186 @@ OpFn OP_TABLE(386)[1024] =
/*d0*/ opD0_a32, opD1_l_a32, opD2_a32, opD3_l_a32, opAAM, opAAD, opSETALC, opXLAT_a32, opESCAPE_d8_a32,opESCAPE_d9_a32,opESCAPE_da_a32,opESCAPE_db_a32,opESCAPE_dc_a32,opESCAPE_dd_a32,opESCAPE_de_a32,opESCAPE_df_a32,
/*e0*/ opLOOPNE_l, opLOOPE_l, opLOOP_l, opJECXZ, opIN_AL_imm, opIN_EAX_imm, opOUT_AL_imm, opOUT_EAX_imm, opCALL_r32, opJMP_r32, opJMP_far_a32, opJMP_r8, opIN_AL_DX, opIN_EAX_DX, opOUT_AL_DX, opOUT_EAX_DX,
/*f0*/ opLOCK, opINT1, opREPNE, opREPE, opHLT, opCMC, opF6_a32, opF7_l_a32, opCLC, opSTC, opCLI, opSTI, opCLD, opSTD, opINCDEC_b_a32, opFF_l_a32,
};
OpFn OP_TABLE(REPE)[1024] =
{
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPE_w_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPE_w_a16,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPE_w_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPE_w_a16,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPE_w_a16,opGS_REPE_w_a16,op_66_REPE, op_67_REPE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a16, opREP_INSW_a16, opREP_OUTSB_a16,opREP_OUTSW_a16,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a16,opREP_MOVSW_a16,opREP_CMPSB_a16_E,opREP_CMPSW_a16_E,ILLEGAL, ILLEGAL, opREP_STOSB_a16,opREP_STOSW_a16,opREP_LODSB_a16,opREP_LODSW_a16,opREP_SCASB_a16_E,opREP_SCASW_a16_E,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPE_l_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPE_l_a16,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPE_l_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPE_l_a16,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPE_l_a16,opGS_REPE_l_a16,op_66_REPE, op_67_REPE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a16, opREP_INSL_a16, opREP_OUTSB_a16,opREP_OUTSL_a16,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a16,opREP_MOVSL_a16,opREP_CMPSB_a16_E,opREP_CMPSL_a16_E,ILLEGAL, ILLEGAL, opREP_STOSB_a16,opREP_STOSL_a16,opREP_LODSB_a16,opREP_LODSL_a16,opREP_SCASB_a16_E,opREP_SCASL_a16_E,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPE_w_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPE_w_a32,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPE_w_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPE_w_a32,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPE_w_a32,opGS_REPE_w_a32,op_66_REPE, op_67_REPE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a32, opREP_INSW_a32, opREP_OUTSB_a32,opREP_OUTSW_a32,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a32,opREP_MOVSW_a32,opREP_CMPSB_a32_E,opREP_CMPSW_a32_E,ILLEGAL, ILLEGAL, opREP_STOSB_a32,opREP_STOSW_a32,opREP_LODSB_a32,opREP_LODSW_a32,opREP_SCASB_a32_E,opREP_SCASW_a32_E,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPE_l_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPE_l_a32,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPE_l_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPE_l_a32,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPE_l_a32,opGS_REPE_l_a32,op_66_REPE, op_67_REPE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a32, opREP_INSL_a32, opREP_OUTSB_a32,opREP_OUTSL_a32,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a32,opREP_MOVSL_a32,opREP_CMPSB_a32_E,opREP_CMPSL_a32_E,ILLEGAL, ILLEGAL, opREP_STOSB_a32,opREP_STOSL_a32,opREP_LODSB_a32,opREP_LODSL_a32,opREP_SCASB_a32_E,opREP_SCASL_a32_E,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
OpFn OP_TABLE(REPNE)[1024] =
{
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPNE_w_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPNE_w_a16,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPNE_w_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPNE_w_a16,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPNE_w_a16,opGS_REPNE_w_a16,op_66_REPNE, op_67_REPNE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a16, opREP_INSW_a16, opREP_OUTSB_a16,opREP_OUTSW_a16,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a16,opREP_MOVSW_a16,opREP_CMPSB_a16_NE,opREP_CMPSW_a16_NE,ILLEGAL, ILLEGAL, opREP_STOSB_a16,opREP_STOSW_a16,opREP_LODSB_a16,opREP_LODSW_a16,opREP_SCASB_a16_NE,opREP_SCASW_a16_NE,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPNE_l_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPNE_l_a16,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPNE_l_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPNE_l_a16,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPNE_l_a16,opGS_REPNE_l_a16,op_66_REPNE, op_67_REPNE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a16, opREP_INSL_a16, opREP_OUTSB_a16,opREP_OUTSL_a16,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a16,opREP_MOVSL_a16,opREP_CMPSB_a16_NE,opREP_CMPSL_a16_NE,ILLEGAL, ILLEGAL, opREP_STOSB_a16,opREP_STOSL_a16,opREP_LODSB_a16,opREP_LODSL_a16,opREP_SCASB_a16_NE,opREP_SCASL_a16_NE,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPNE_w_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPNE_w_a32,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPNE_w_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPNE_w_a32,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPNE_w_a32,opGS_REPNE_w_a32,op_66_REPNE, op_67_REPNE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a32, opREP_INSW_a32, opREP_OUTSB_a32,opREP_OUTSW_a32,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a32,opREP_MOVSW_a32,opREP_CMPSB_a32_NE,opREP_CMPSW_a32_NE,ILLEGAL, ILLEGAL, opREP_STOSB_a32,opREP_STOSW_a32,opREP_LODSB_a32,opREP_LODSW_a32,opREP_SCASB_a32_NE,opREP_SCASW_a32_NE,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opES_REPNE_l_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opCS_REPNE_l_a32,ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSS_REPNE_l_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opDS_REPNE_l_a32,ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opFS_REPNE_l_a32,opGS_REPNE_l_a32,op_66_REPNE, op_67_REPNE, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_INSB_a32, opREP_INSL_a32, opREP_OUTSB_a32,opREP_OUTSL_a32,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*a0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opREP_MOVSB_a32,opREP_MOVSL_a32,opREP_CMPSB_a32_NE,opREP_CMPSL_a32_NE,ILLEGAL, ILLEGAL, opREP_STOSB_a32,opREP_STOSL_a32,opREP_LODSB_a32,opREP_LODSL_a32,opREP_SCASB_a32_NE,opREP_SCASL_a32_NE,
/*b0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};

94
src/CPU/codegen_ops.c
View File

@@ -496,3 +496,97 @@ RecompOpFn recomp_opcodes_df[512] =
/*e0*/ ropFSTSW_AX, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
RecompOpFn recomp_opcodes_REPE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
RecompOpFn recomp_opcodes_REPNE[512] =
{
/*16-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*32-bit data*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*10*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*20*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*30*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*40*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*50*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*60*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*70*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*80*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*90*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*a0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*b0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*c0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*d0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*e0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
/*f0*/ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};

2
src/CPU/codegen_ops.h
View File

@@ -10,6 +10,8 @@ extern RecompOpFn recomp_opcodes_dc[512];
extern RecompOpFn recomp_opcodes_dd[512];
extern RecompOpFn recomp_opcodes_de[512];
extern RecompOpFn recomp_opcodes_df[512];
RecompOpFn recomp_opcodes_REPE[512];
RecompOpFn recomp_opcodes_REPNE[512];
#define REG_EAX 0
#define REG_ECX 1

16
src/CPU/codegen_x86-64.c
View File

@@ -1049,6 +1049,15 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
break;
case 0xf3: /*REPE*/
op_table = x86_dynarec_opcodes_REPE;
recomp_op_table = recomp_opcodes_REPE;
break;
default:
goto generate_call;
}
@@ -1089,6 +1098,13 @@ generate_call:
codegen_block_ins = 0;
}
}
if ((op_table == x86_opcodes_REPNE || op_table == x86_opcodes_REPE) && !op_table[opcode | op_32])
{
op_table = x86_dynarec_opcodes;
recomp_op_table = recomp_opcodes;
}
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff])
{
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);

15
src/CPU/codegen_x86.c
View File

@@ -1977,6 +1977,15 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
case 0xf0: /*LOCK*/
break;
case 0xf2: /*REPNE*/
op_table = x86_dynarec_opcodes_REPNE;
recomp_op_table = recomp_opcodes_REPNE;
break;
case 0xf3: /*REPE*/
op_table = x86_dynarec_opcodes_REPE;
recomp_op_table = recomp_opcodes_REPE;
break;
default:
goto generate_call;
@@ -2030,6 +2039,12 @@ generate_call:
#endif
}
if ((op_table == x86_opcodes_REPNE || op_table == x86_opcodes_REPE) && !op_table[opcode | op_32])
{
op_table = x86_dynarec_opcodes;
recomp_op_table = recomp_opcodes;
}
if (recomp_op_table && recomp_op_table[(opcode | op_32) & 0x1ff])
{
uint32_t new_pc = recomp_op_table[(opcode | op_32) & 0x1ff](opcode, fetchdat, op_32, op_pc, block);

8
src/CPU/cpu.c
View File

@@ -48,6 +48,8 @@ OpFn *x86_dynarec_opcodes_de_a16;
OpFn *x86_dynarec_opcodes_de_a32;
OpFn *x86_dynarec_opcodes_df_a16;
OpFn *x86_dynarec_opcodes_df_a32;
OpFn *x86_dynarec_opcodes_REPE;
OpFn *x86_dynarec_opcodes_REPNE;
OpFn *x86_opcodes;
OpFn *x86_opcodes_0f;
@@ -67,6 +69,8 @@ OpFn *x86_opcodes_de_a16;
OpFn *x86_opcodes_de_a32;
OpFn *x86_opcodes_df_a16;
OpFn *x86_opcodes_df_a32;
OpFn *x86_opcodes_REPE;
OpFn *x86_opcodes_REPNE;
enum
{
@@ -679,6 +683,10 @@ void cpu_set()
pclog("is486 - %i %i\n",is486,cpu_s->cpu_type);
x86_setopcodes(ops_386, ops_386_0f, dynarec_ops_386, dynarec_ops_386_0f);
x86_opcodes_REPE = ops_REPE;
x86_opcodes_REPNE = ops_REPNE;
x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
if (hasfpu)
{

10
src/CPU/x86_ops.h
View File

@@ -26,6 +26,8 @@ extern OpFn *x86_dynarec_opcodes_de_a16;
extern OpFn *x86_dynarec_opcodes_de_a32;
extern OpFn *x86_dynarec_opcodes_df_a16;
extern OpFn *x86_dynarec_opcodes_df_a32;
extern OpFn *x86_dynarec_opcodes_REPE;
extern OpFn *x86_dynarec_opcodes_REPNE;
extern OpFn dynarec_ops_286[1024];
extern OpFn dynarec_ops_286_0f[1024];
@@ -87,6 +89,9 @@ extern OpFn dynarec_ops_fpu_686_db_a32[256];
extern OpFn dynarec_ops_fpu_686_df_a16[256];
extern OpFn dynarec_ops_fpu_686_df_a32[256];
extern OpFn dynarec_ops_REPE[1024];
extern OpFn dynarec_ops_REPNE[1024];
extern OpFn *x86_opcodes;
extern OpFn *x86_opcodes_0f;
extern OpFn *x86_opcodes_d8_a16;
@@ -105,6 +110,8 @@ extern OpFn *x86_opcodes_de_a16;
extern OpFn *x86_opcodes_de_a32;
extern OpFn *x86_opcodes_df_a16;
extern OpFn *x86_opcodes_df_a32;
extern OpFn *x86_opcodes_REPE;
extern OpFn *x86_opcodes_REPNE;
extern OpFn ops_286[1024];
extern OpFn ops_286_0f[1024];
@@ -167,4 +174,7 @@ extern OpFn ops_fpu_686_db_a32[256];
extern OpFn ops_fpu_686_df_a16[256];
extern OpFn ops_fpu_686_df_a32[256];
extern OpFn ops_REPE[1024];
extern OpFn ops_REPNE[1024];
#endif /*_X86_OPS_H*/

97
src/CPU/x86_ops_prefix.h
View File

@@ -1,4 +1,4 @@
#define op_seg(name, seg) \
#define op_seg(name, seg, opcode_table, normal_opcode_table) \
static int op ## name ## _w_a16(uint32_t fetchdat) \
{ \
fetchdat = fastreadl(cs + cpu_state.pc); \
@@ -10,7 +10,9 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[fetchdat & 0xff](fetchdat >> 8); \
if (opcode_table[fetchdat & 0xff]) \
return opcode_table[fetchdat & 0xff](fetchdat >> 8); \
return normal_opcode_table[fetchdat & 0xff](fetchdat >> 8); \
} \
\
static int op ## name ## _l_a16(uint32_t fetchdat) \
@@ -24,7 +26,9 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
if (opcode_table[(fetchdat & 0xff) | 0x100]) \
return opcode_table[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
return normal_opcode_table[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
} \
\
static int op ## name ## _w_a32(uint32_t fetchdat) \
@@ -38,7 +42,9 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
if (opcode_table[(fetchdat & 0xff) | 0x200]) \
return opcode_table[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
return normal_opcode_table[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
} \
\
static int op ## name ## _l_a32(uint32_t fetchdat) \
@@ -52,15 +58,31 @@ static int op ## name ## _l_a32(uint32_t fetchdat) \
CLOCK_CYCLES(4); \
PREFETCH_PREFIX(); \
\
return x86_opcodes[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
if (opcode_table[(fetchdat & 0xff) | 0x300]) \
return opcode_table[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
return normal_opcode_table[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
}
op_seg(CS, _cs)
op_seg(DS, _ds)
op_seg(ES, _es)
op_seg(FS, _fs)
op_seg(GS, _gs)
op_seg(SS, _ss)
op_seg(CS, _cs, x86_opcodes, x86_opcodes)
op_seg(DS, _ds, x86_opcodes, x86_opcodes)
op_seg(ES, _es, x86_opcodes, x86_opcodes)
op_seg(FS, _fs, x86_opcodes, x86_opcodes)
op_seg(GS, _gs, x86_opcodes, x86_opcodes)
op_seg(SS, _ss, x86_opcodes, x86_opcodes)
op_seg(CS_REPE, _cs, x86_opcodes_REPE, x86_opcodes)
op_seg(DS_REPE, _ds, x86_opcodes_REPE, x86_opcodes)
op_seg(ES_REPE, _es, x86_opcodes_REPE, x86_opcodes)
op_seg(FS_REPE, _fs, x86_opcodes_REPE, x86_opcodes)
op_seg(GS_REPE, _gs, x86_opcodes_REPE, x86_opcodes)
op_seg(SS_REPE, _ss, x86_opcodes_REPE, x86_opcodes)
op_seg(CS_REPNE, _cs, x86_opcodes_REPNE, x86_opcodes)
op_seg(DS_REPNE, _ds, x86_opcodes_REPNE, x86_opcodes)
op_seg(ES_REPNE, _es, x86_opcodes_REPNE, x86_opcodes)
op_seg(FS_REPNE, _fs, x86_opcodes_REPNE, x86_opcodes)
op_seg(GS_REPNE, _gs, x86_opcodes_REPNE, x86_opcodes)
op_seg(SS_REPNE, _ss, x86_opcodes_REPNE, x86_opcodes)
static int op_66(uint32_t fetchdat) /*Data size select*/
{
@@ -84,3 +106,56 @@ static int op_67(uint32_t fetchdat) /*Address size select*/
PREFETCH_PREFIX();
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int op_66_REPE(uint32_t fetchdat) /*Data size select*/
{
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int op_67_REPE(uint32_t fetchdat) /*Address size select*/
{
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int op_66_REPNE(uint32_t fetchdat) /*Data size select*/
{
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
cpu_state.op32 = ((use32 & 0x100) ^ 0x100) | (cpu_state.op32 & 0x200);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int op_67_REPNE(uint32_t fetchdat) /*Address size select*/
{
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
cpu_state.op32 = ((use32 & 0x200) ^ 0x200) | (cpu_state.op32 & 0x100);
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}

629
src/CPU/x86_ops_rep.h
View File

@@ -1,12 +1,629 @@
/* Copyright holders: Sarah Walker
see COPYING for more details
*/
#define REP_OPS(size, CNT_REG, SRC_REG, DEST_REG) \
static int opREP_INSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint8_t temp; \
\
check_io_perm(DX); \
temp = inb(DX); \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_INSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint16_t temp; \
\
check_io_perm(DX); \
check_io_perm(DX+1); \
temp = inw(DX); \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_INSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint32_t temp; \
\
check_io_perm(DX); \
check_io_perm(DX+1); \
check_io_perm(DX+2); \
check_io_perm(DX+3); \
temp = inl(DX); \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
\
static int opREP_OUTSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
outb(DX, temp); \
if (flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_OUTSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
outw(DX, temp); \
if (flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_OUTSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
check_io_perm(DX+2); \
check_io_perm(DX+3); \
outl(DX, temp); \
if (flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
\
static int opREP_MOVSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
uint8_t temp; \
\
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_MOVSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
uint16_t temp; \
\
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_MOVSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
uint32_t temp; \
\
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
\
\
static int opREP_STOSB_ ## size(uint32_t fetchdat) \
{ \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG); \
writememb(es, DEST_REG, AL); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_STOSW_ ## size(uint32_t fetchdat) \
{ \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+1); \
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_STOSL_ ## size(uint32_t fetchdat) \
{ \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&_es, DEST_REG, DEST_REG+3); \
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
\
static int opREP_LODSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_LODSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_LODSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
while (CNT_REG > 0) \
{ \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
#define REP_OPS_CMPS_SCAS(size, CNT_REG, SRC_REG, DEST_REG, FV) \
static int opREP_CMPSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint8_t temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
uint8_t temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
setsub8(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_CMPSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint16_t temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
uint16_t temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
setsub16(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_CMPSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint32_t temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
uint32_t temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
\
if (flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
setsub32(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
\
static int opREP_SCASB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
tempz = FV; \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint8_t temp = readmemb(es, DEST_REG); if (cpu_state.abrt) break;\
setsub8(AL, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_SCASW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
tempz = FV; \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
setsub16(AX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_SCASL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
\
tempz = FV; \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
setsub32(EAX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
}
REP_OPS(a16, CX, SI, DI)
REP_OPS(a32, ECX, ESI, EDI)
REP_OPS_CMPS_SCAS(a16_NE, CX, SI, DI, 0)
REP_OPS_CMPS_SCAS(a16_E, CX, SI, DI, 1)
REP_OPS_CMPS_SCAS(a32_NE, ECX, ESI, EDI, 0)
REP_OPS_CMPS_SCAS(a32_E, ECX, ESI, EDI, 1)
static int opREPNE(uint32_t fetchdat)
{
return rep386(0);
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPNE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}
static int opREPE(uint32_t fetchdat)
{
return rep386(1);
}
fetchdat = fastreadl(cs + cpu_state.pc);
if (cpu_state.abrt) return 1;
cpu_state.pc++;
CLOCK_CYCLES(2);
PREFETCH_PREFIX();
if (x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32])
return x86_opcodes_REPE[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
return x86_opcodes[(fetchdat & 0xff) | cpu_state.op32](fetchdat >> 8);
}

1
src/ibm.h
View File

@@ -775,7 +775,6 @@ extern void pmodeiret(int is32);
extern void port_92_clear_reset(void);
extern uint8_t readdacfifo(void);
extern void refreshread(void);
extern int rep386(int fv);
extern void resetmcr(void);
extern void resetpchard_close(void);
extern void resetpchard_init(void);