Named initializers for soclet 3's
This commit is contained in:
Jasmine Iwanek
@@ -2543,8 +2543,40 @@ const cpu_family_t cpu_families[] = {
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.name = "Pentium OverDrive",
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.internal_name = "pentium_p24t",
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.cpus = (const CPU[]) {
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{"63", CPU_P24T, fpus_internal, 62500000, 2.5, 5000, 0x1531, 0x1531, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
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{"83", CPU_P24T, fpus_internal, 83333333, 2.5, 5000, 0x1532, 0x1532, 0x0000, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
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{
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.name = "63",
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.cpu_type = CPU_P24T,
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.fpus = fpus_internal,
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.rspeed = 62500000,
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.multi = 2.5,
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.voltage = 5000,
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.edx_reset = 0x1531,
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.cpuid_model = 0x1531,
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.cyrix_id = 0x0000,
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.cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,
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.mem_read_cycles = 10,
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.mem_write_cycles = 10,
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.cache_read_cycles = 7,
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.cache_write_cycles = 7,
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.atclk_div = 15/2
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},
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{
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.name = "83",
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.cpu_type = CPU_P24T,
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.fpus = fpus_internal,
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.rspeed = 83333333,
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.multi = 2.5,
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.voltage = 5000,
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.edx_reset = 0x1532,
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.cpuid_model = 0x1532,
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.cyrix_id = 0x0000,
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.cpu_flags = CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC,
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.mem_read_cycles = 15,
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.mem_write_cycles = 15,
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.cache_read_cycles = 8,
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.cache_write_cycles = 8,
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.atclk_div = 10
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},
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{ .name = "", 0 }
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}
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},
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@@ -2846,10 +2878,74 @@ const cpu_family_t cpu_families[] = {
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.name = "Am486DX4",
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.internal_name = "am486dx4",
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.cpus = (const CPU[]) {
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{"75", CPU_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
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{"90", CPU_Am486DX, fpus_internal, 90000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
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{"100", CPU_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
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{"120", CPU_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x432, 0, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
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{
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.name = "75",
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.cpu_type = CPU_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 75000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x432,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 12,
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.mem_write_cycles = 12,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 9
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},
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{
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.name = "90",
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.cpu_type = CPU_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 90000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x432,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 15,
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.mem_write_cycles = 15,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 12
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},
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{
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.name = "100",
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.cpu_type = CPU_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 100000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x432,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 15,
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.mem_write_cycles = 15,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 12
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},
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{
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.name = "120",
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.cpu_type = CPU_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 120000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x432,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 21,
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.mem_write_cycles = 21,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 15
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},
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{ .name = "", 0 }
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}
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},
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@@ -2859,8 +2955,40 @@ const cpu_family_t cpu_families[] = {
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.name = "Am486DX2 (Enhanced)",
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.internal_name = "am486dx2_slenh",
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.cpus = (const CPU[]) {
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{"66", CPU_ENH_Am486DX, fpus_internal, 66666666, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8},
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{"80", CPU_ENH_Am486DX, fpus_internal, 80000000, 2, 5000, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
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{
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.name = "66",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 66666666,
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.multi = 2,
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.voltage = 5000,
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.edx_reset = 0x435,
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.cpuid_model = 0x435,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 12,
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.mem_write_cycles = 12,
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.cache_read_cycles = 6,
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.cache_write_cycles = 6,
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.atclk_div = 8
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},
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{
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.name = "80",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 80000000,
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.multi = 2,
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.voltage = 5000,
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.edx_reset = 0x435,
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.cpuid_model = 0x435,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 14,
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.mem_write_cycles = 14,
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.cache_read_cycles = 6,
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.cache_write_cycles = 6,
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.atclk_div = 10
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},
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{ .name = "", 0 }
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}
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},
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@@ -2870,9 +2998,57 @@ const cpu_family_t cpu_families[] = {
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.name = "Am486DX4 (Enhanced)",
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.internal_name = "am486dx4_slenh",
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.cpus = (const CPU[]) {
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{"75", CPU_ENH_Am486DX, fpus_internal, 75000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
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{"100", CPU_ENH_Am486DX, fpus_internal, 100000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
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{"120", CPU_ENH_Am486DX, fpus_internal, 120000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
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{
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.name = "75",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 75000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x482,
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.cpuid_model = 0x482,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 12,
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.mem_write_cycles = 12,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 9
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},
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{
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.name = "100",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 100000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x482,
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.cpuid_model = 0x482,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 15,
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.mem_write_cycles = 15,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 12
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},
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{
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.name = "120",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 120000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x482,
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.cpuid_model = 0x482,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 21,
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.mem_write_cycles = 21,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 15
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},
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{ .name = "", 0 }
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}
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},
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@@ -2882,9 +3058,57 @@ const cpu_family_t cpu_families[] = {
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.name = "Am5x86",
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.internal_name = "am5x86",
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.cpus = (const CPU[]) {
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{"133 (P75)", CPU_ENH_Am486DX, fpus_internal, 133333333, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
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{"150 (P75+)", CPU_ENH_Am486DX, fpus_internal, 150000000, 3.0, 5000, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
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{"160 (P90)", CPU_ENH_Am486DX, fpus_internal, 160000000, 4.0, 5000, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
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{
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.name = "133 (P75)",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 133333333,
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.multi = 4.0,
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.voltage = 5000,
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.edx_reset = 0x4e0,
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.cpuid_model = 0x4e0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 24,
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.mem_write_cycles = 24,
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.cache_read_cycles = 12,
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.cache_write_cycles = 12,
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.atclk_div = 16
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},
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{ /*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/
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.name = "150 (P75+)",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 150000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x482,
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.cpuid_model = 0x482,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 28,
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.mem_write_cycles = 28,
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.cache_read_cycles = 12,
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.cache_write_cycles = 12,
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.atclk_div = 20
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},
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{ /*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/
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.name = "160 (P90)",
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.cpu_type = CPU_ENH_Am486DX,
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.fpus = fpus_internal,
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.rspeed = 160000000,
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.multi = 4.0,
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.voltage = 5000,
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.edx_reset = 0x4e0,
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.cpuid_model = 0x4e0,
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.cyrix_id = 0,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 28,
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.mem_write_cycles = 28,
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.cache_read_cycles = 12,
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.cache_write_cycles = 12,
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.atclk_div = 20
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},
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{ .name = "", 0 }
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}
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},
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@@ -3057,8 +3281,12 @@ const cpu_family_t cpu_families[] = {
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.name = "Cx486DX4",
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.internal_name = "cx486dx4",
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.cpus = (const CPU[]) {
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{"75", CPU_Cx486DX, fpus_internal, 75000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9},
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{"100", CPU_Cx486DX, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
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{
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.name = "75", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 75000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 12,.mem_write_cycles = 12, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 9
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},
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{
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.name = "100", .cpu_type = CPU_Cx486DX, .fpus = fpus_internal, .rspeed = 100000000, .multi = 3.0, .voltage = 5000, .edx_reset = 0x480, .cpuid_model = 0, .cyrix_id = 0x361f, .cpu_flags = CPU_SUPPORTS_DYNAREC, .mem_read_cycles = 15,.mem_write_cycles = 15, .cache_read_cycles = 9, .cache_write_cycles = 9, .atclk_div = 12
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},
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{ .name = "", 0 }
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}
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},
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@@ -3068,10 +3296,74 @@ const cpu_family_t cpu_families[] = {
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.name = "Cx5x86",
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.internal_name = "cx5x86",
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.cpus = (const CPU[]) {
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{"80", CPU_Cx5x86, fpus_internal, 80000000, 2.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/
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{"100", CPU_Cx5x86, fpus_internal, 100000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12},
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{"120", CPU_Cx5x86, fpus_internal, 120000000, 3.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15},
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{"133", CPU_Cx5x86, fpus_internal, 133333333, 4.0, 5000, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16},
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{ /*If we're including the Pentium 50, might as well include this*/
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.name = "80",
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.cpu_type = CPU_Cx5x86,
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.fpus = fpus_internal,
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.rspeed = 80000000,
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.multi = 2.0,
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.voltage = 5000,
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.edx_reset = 0x480,
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.cpuid_model = 0,
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.cyrix_id = 0x002f,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 14,
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.mem_write_cycles = 14,
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.cache_read_cycles = 6,
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.cache_write_cycles = 6,
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.atclk_div = 10
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},
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{
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.name = "100",
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.cpu_type = CPU_Cx5x86,
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.fpus = fpus_internal,
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.rspeed = 100000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x480,
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.cpuid_model = 0,
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.cyrix_id = 0x002f,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 15,
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.mem_write_cycles = 15,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 12
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},
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{
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.name = "120",
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.cpu_type = CPU_Cx5x86,
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.fpus = fpus_internal,
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.rspeed = 120000000,
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.multi = 3.0,
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.voltage = 5000,
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.edx_reset = 0x480,
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.cpuid_model = 0,
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.cyrix_id = 0x002f,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 21,
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.mem_write_cycles = 21,
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.cache_read_cycles = 9,
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.cache_write_cycles = 9,
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.atclk_div = 15
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},
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{
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.name = "133",
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.cpu_type = CPU_Cx5x86,
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.fpus = fpus_internal,
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.rspeed = 133333333,
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.multi = 4.0,
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.voltage = 5000,
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.edx_reset = 0x480,
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.cpuid_model = 0,
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.cyrix_id = 0x002f,
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.cpu_flags = CPU_SUPPORTS_DYNAREC,
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.mem_read_cycles = 24,
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.mem_write_cycles = 24,
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.cache_read_cycles = 12,
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.cache_write_cycles = 12,
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.atclk_div = 16
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},
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{ .name = "", 0 }
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}
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},
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