80486DX2-66/86Box-fork
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More fixes, fixes CMOS Setup on the Acrosses AR-B4179.

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This commit is contained in:
OBattler
2021-08-09 16:10:55 +02:00
parent 0d5c5f361a
commit f0e84f7f13
4 changed files with 7 additions and 5 deletions
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2
src/chipset/stpc.c
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@@ -150,7 +150,7 @@ stpc_recalcmapping(stpc_t *dev)
} }
} }
flushmmucache(); flushmmucache_nopc();
} }

1
src/cpu/386_common.c
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@@ -306,6 +306,7 @@ enum SMMRAM_Fields_AMD_K {
}; };
#define ENABLE_386_COMMON_LOG 1
#ifdef ENABLE_386_COMMON_LOG #ifdef ENABLE_386_COMMON_LOG
int x386_common_do_log = ENABLE_386_COMMON_LOG; int x386_common_do_log = ENABLE_386_COMMON_LOG;

7
src/cpu/cpu.c
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@@ -375,7 +375,7 @@ cpu_set(void)
is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL); is_am486dxl = (cpu_s->cpu_type == CPU_Am486DXL);
cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel"); cpu_isintel = !strcmp(cpu_f->manufacturer, "Intel");
cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix"); cpu_iscyrix = !strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST");
/* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums, /* SL-Enhanced Intel 486s have the same SMM save state table layout as Pentiums,
and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/ and the WinChip datasheet claims those are Pentium-compatible as well. AMD Am486DXL/DXL2 also has compatible SMM, or would if not for it's different SMBase*/
@@ -385,7 +385,8 @@ cpu_set(void)
is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD"); is_k6 = (cpu_s->cpu_type >= CPU_K6) && !strcmp(cpu_f->manufacturer, "AMD");
/* The Samuel 2 datasheet claims it's Celeron-compatible. */ /* The Samuel 2 datasheet claims it's Celeron-compatible. */
is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA"); is_p6 = (cpu_isintel && (cpu_s->cpu_type >= CPU_PENTIUMPRO)) || !strcmp(cpu_f->manufacturer, "VIA");
is_cxsmm = !strcmp(cpu_f->manufacturer, "Cyrix") && (cpu_s->cpu_type >= CPU_Cx486S); is_cxsmm = (!strcmp(cpu_f->manufacturer, "Cyrix") || !strcmp(cpu_f->manufacturer, "ST")) &&
(cpu_s->cpu_type >= CPU_Cx486S);
hasfpu = (fpu_type != FPU_NONE); hasfpu = (fpu_type != FPU_NONE);
hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) || hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC) ||
@@ -2962,7 +2963,7 @@ cpu_read(uint16_t addr, void *priv)
if ((cyrix_addr & 0xf0) == 0xc0) if ((cyrix_addr & 0xf0) == 0xc0)
return 0xff; return 0xff;
if (cyrix_addr == 0x20 && cpu_s->cpu_type == CPU_Cx5x86) if (cyrix_addr == 0x20 && (cpu_s->cpu_type == CPU_Cx5x86))
return 0xff; return 0xff;
} }

2
src/cpu/cpu_table.c
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@@ -586,7 +586,7 @@ const cpu_family_t cpu_families[] = {
.name = "STPC-DX2", .name = "STPC-DX2",
.internal_name = "stpc_dx2", .internal_name = "stpc_dx2",
.cpus = (const CPU[]) { .cpus = (const CPU[]) {
{"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, {"133", CPU_STPC, fpus_internal, 133333333, 2.0, 3300, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10},
{"", 0} {"", 0}
} }
}, { }, {