80486DX2-66/86Box-fork
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More RTL8029AS fixes from TheCollector1995;

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FDC now updates the floppy drive's DENSEL on receiving updates from the Super I/O chip;
Commented out ASIS P/I-P55TP4XE and ASUS P/I-P55T2P4 because they are too buggy;
Completely illegal instructions now also log the second byte for purposes of prefixed instruction identification;
PIC now sets mask to 0 on reset.
This commit is contained in:
OBattler
2016-08-13 17:29:14 +02:00
parent 91075fb627
commit f1367357b0
5 changed files with 52 additions and 23 deletions
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8
src/386_ops.h
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@@ -153,12 +153,14 @@ static inline uint32_t POP_L_seg(uint32_t seg)
#include "x86_ops_string.h"
#include "x86_ops_xchg.h"
static int fopcode;
static int ILLEGAL(uint32_t fetchdat)
{
cpu_state.pc = oldpc;
// fatal("Illegal instruction %08X\n", fetchdat);
pclog("Illegal instruction %08X\n", fetchdat);
pclog("Illegal instruction %08X (%02X)\n", fetchdat, fopcode);
x86illegal();
return 0;
}
@@ -166,6 +168,7 @@ static int ILLEGAL(uint32_t fetchdat)
static int op0F_w_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
cpu_state.pc++;
// pclog("A16W: 0F %02X\n", opcode);
@@ -174,6 +177,7 @@ static int op0F_w_a16(uint32_t fetchdat)
static int op0F_l_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
cpu_state.pc++;
// pclog("A16L: 0F %02X\n", opcode);
@@ -182,6 +186,7 @@ static int op0F_l_a16(uint32_t fetchdat)
static int op0F_w_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
cpu_state.pc++;
// pclog("A32W: 0F %02X\n", opcode);
@@ -190,6 +195,7 @@ static int op0F_w_a32(uint32_t fetchdat)
static int op0F_l_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
cpu_state.pc++;
// pclog("A32L: 0F %02X\n", opcode);

9
src/fdc.c
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@@ -184,14 +184,18 @@ void fdc_update_enh_mode(int enh_mode)
fdc.enh_mode = enh_mode;
}
static void fdc_rate(int drive);
int fdc_get_rwc(int drive)
{
return fdc.rwc[drive];
fdc_rate(drive);
}
void fdc_update_rwc(int drive, int rwc)
{
fdc.rwc[drive] = rwc;
fdc_rate(drive);
}
int fdc_get_boot_drive()
@@ -207,16 +211,21 @@ void fdc_update_boot_drive(int boot_drive)
void fdc_update_densel_polarity(int densel_polarity)
{
fdc.densel_polarity = densel_polarity;
fdc_rate(0);
fdc_rate(1);
}
void fdc_update_densel_force(int densel_force)
{
fdc.densel_force = densel_force;
fdc_rate(0);
fdc_rate(1);
}
void fdc_update_drvrate(int drive, int drvrate)
{
fdc.drvrate[drive] = drvrate;
fdc_rate(drive);
}
void fdc_update_drv2en(int drv2en)

12
src/model.c
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@@ -88,10 +88,10 @@ void at_r418_init();
void at_586mc1_init();
void at_plato_init();
void at_mb500n_init();
void at_p54tp4xe_init();
// void at_p54tp4xe_init();
void at_acerm3a_init();
void at_acerv35n_init();
void at_p55t2p4_init();
// void at_p55t2p4_init();
void at_p55tvp4_init();
void at_p55va_init();
void at_i440fx_init();
@@ -149,10 +149,10 @@ MODEL models[] =
{"Intel Premiere/PCI II",ROM_PLATO, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 128, 1, at_plato_init},
{"Intel Advanced/EV", ROM_ENDEAVOR, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 128, 1, at_endeavor_init},
{"PC Partner MB500N", ROM_MB500N, { "Intel", cpus_PentiumS5,"IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 128, 1, at_mb500n_init},
{"ASUS P/I-P54TP4XE", ROM_P54TP4XE, { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 512, 1, at_p54tp4xe_init},
// {"ASUS P/I-P54TP4XE", ROM_P54TP4XE, { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL}, 0, 1, 1, 512, 1, at_p54tp4xe_init},
{"Acer M3a", ROM_ACERM3A, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_acerm3a_init},
{"Acer V35N", ROM_ACERV35N, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_acerv35n_init},
{"ASUS P/I-P55T2P4", ROM_P55T2P4, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_p55t2p4_init},
// {"ASUS P/I-P55T2P4", ROM_P55T2P4, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_p55t2p4_init},
{"Award 430VX PCI", ROM_430VX, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 256, 1, at_i430vx_init},
{"ASUS P/I-P55TVP4", ROM_P55TVP4, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 512, 1, at_p55tvp4_init},
{"Epox P55-VA", ROM_P55VA, { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, 1, 1, 256, 1, at_p55va_init},
@@ -499,6 +499,7 @@ void at_mb500n_init()
if (cdrom_channel >= 4) ide_ter_init();
}
#if 0
void at_p54tp4xe_init()
{
at_init();
@@ -512,6 +513,7 @@ void at_p54tp4xe_init()
device_add(&intel_flash_bxt_device);
if (cdrom_channel >= 4) ide_ter_init();
}
#endif
void at_acerm3a_init()
{
@@ -539,6 +541,7 @@ void at_acerv35n_init()
if (cdrom_channel >= 4) ide_ter_init();
}
#if 0
void at_p55t2p4_init()
{
at_init();
@@ -551,6 +554,7 @@ void at_p55t2p4_init()
device_add(&intel_flash_bxt_device);
if (cdrom_channel >= 4) ide_ter_init();
}
#endif
void at_i430vx_init()
{

40
src/ne2000.c
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@@ -39,6 +39,7 @@
#include "ibm.h"
#include "device.h"
#include "config.h"
#include "nethandler.h"
#include "io.h"
@@ -878,7 +879,7 @@ void ne2000_page0_write(ne2000_t *ne2000, uint32_t offset, uint32_t value, unsig
// Auto-transmit disable very suspicious
if (value & 0x08)
pclog("TCR write, auto transmit disable not supported\m");
pclog("TCR write, auto transmit disable not supported\n");
// Allow collision-offset to be set, although not used
ne2000->TCR.coll_prio = ((value & 0x08) == 0x08);
@@ -1462,13 +1463,13 @@ void ne2000_rx_frame(void *p, const void *buf, int io_len)
}
uint8_t ne2000_readb(uint32_t addr, void *p)
uint8_t ne2000_readb(uint16_t addr, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
return ne2000_read(ne2000, addr, 1);
}
uint16_t ne2000_readw(uint32_t addr, void *p)
uint16_t ne2000_readw(uint16_t addr, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
if (ne2000->DCR.wdsize & 1)
@@ -1477,19 +1478,19 @@ uint16_t ne2000_readw(uint32_t addr, void *p)
return ne2000_read(ne2000, addr, 1);
}
uint32_t ne2000_readl(uint32_t addr, void *p)
uint32_t ne2000_readl(uint16_t addr, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
return ne2000_read(ne2000, addr, 4);
}
void ne2000_writeb(uint32_t addr, uint8_t val, void *p)
void ne2000_writeb(uint16_t addr, uint8_t val, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
ne2000_write(ne2000, addr, val, 1);
}
void ne2000_writew(uint32_t addr, uint16_t val, void *p)
void ne2000_writew(uint16_t addr, uint16_t val, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
if (ne2000->DCR.wdsize & 1)
@@ -1498,7 +1499,7 @@ void ne2000_writew(uint32_t addr, uint16_t val, void *p)
ne2000_write(ne2000, addr, val, 1);
}
void ne2000_writel(uint32_t addr, uint32_t val, void *p)
void ne2000_writel(uint16_t addr, uint32_t val, void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
ne2000_write(ne2000, addr, val, 4);
@@ -1558,23 +1559,25 @@ uint8_t ne2000_pci_regs[256];
bar_t ne2000_pci_bar[2];
int bios_addr = 0xD0000;
uint32_t bios_addr = 0xD0000;
uint32_t old_base_addr = 0;
uint32_t bios_size = 0;
uint32_t bios_mask = 0;
void ne2000_io_set(uint16_t addr, ne2000_t *ne2000)
{
old_base_addr = addr;
io_sethandler(addr, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_sethandler(addr+0x10, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_sethandler(addr+0x1f, 0x0001, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writeb, ne2000_writel, ne2000);
io_sethandler(addr+0x1f, 0x0001, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
}
void ne2000_io_remove(uint16_t addr, ne2000_t *ne2000)
void ne2000_io_remove(ne2000_t *ne2000)
{
io_removehandler(addr, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_removehandler(addr+0x10, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_removehandler(addr+0x1f, 0x0001, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_removehandler(old_base_addr, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_removehandler(old_base_addr+0x10, 0x0010, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
io_removehandler(old_base_addr+0x1f, 0x0001, ne2000_readb, ne2000_readw, ne2000_readl, ne2000_writeb, ne2000_writew, ne2000_writel, ne2000);
}
uint8_t ne2000_pci_read(int func, int addr, void *p)
@@ -1654,9 +1657,14 @@ void ne2000_pci_write(int func, int addr, uint8_t val, void *p)
{
case 0x04:
if (val & PCI_COMMAND_IO)
{
ne2000_io_remove(ne2000);
ne2000_io_set(ne2000->base_address, ne2000);
}
else
ne2000_io_remove(ne2000->base_address, ne2000);
{
ne2000_io_remove(ne2000);
}
break;
case 0x10:
@@ -1665,7 +1673,7 @@ void ne2000_pci_write(int func, int addr, uint8_t val, void *p)
case 0x11: case 0x12: case 0x13:
/* I/O Base set. */
/* First, remove the old I/O, if old base was >= 0x280. */
ne2000_io_remove(ne2000->base_address, ne2000);
ne2000_io_remove(ne2000);
/* Then let's set the PCI regs. */
ne2000_pci_bar[0].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
@@ -2119,7 +2127,7 @@ return ne2000;
void ne2000_close(void *p)
{
ne2000_t *ne2000 = (ne2000_t *)p;
ne2000_io_remove(ne2000->base_address, ne2000);
ne2000_io_remove(ne2000);
free(ne2000);
if(net_is_slirp) {

6
src/pic.c
View File

@@ -24,13 +24,15 @@ void pic_updatepending()
void pic_reset()
{
pic.icw=0;
pic.mask=0xFF;
// pic.mask=0xFF;
pic.mask=0;
pic.mask2=0;
pic.pend=pic.ins=0;
pic.vector=8;
pic.read=1;
pic2.icw=0;
pic2.mask=0xFF;
// pic2.mask=0xFF;
pic2.mask=0;
pic.mask2=0;
pic2.pend=pic2.ins=0;
pic_intpending = 0;