Merge pull request #858 from tiseno100/master
Implemented the AMD 640 chipset
This commit is contained in:
Miran Grča
GitHub
230
src/chipset/amd640.c
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230
src/chipset/amd640.c
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@@ -0,0 +1,230 @@
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/*
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*
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* 86Box: A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* <This file is part of the 86Box distribution.>
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*
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* Basic AMD 640 North Bridge emulation
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*
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* Looks similar to the VIA VP2
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* while it's southbridge(AMD-645) is just a 586B [TODO: Probs write it if it has differences]
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*
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* Copyright(C) 2020 Tiseno100
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*
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/mem.h>
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#include <86box/io.h>
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#include <86box/rom.h>
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#include <86box/pci.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/chipset.h>
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typedef struct amd640_t {
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uint8_t regs[256];
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} amd640_t;
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static void
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amd640_map(uint32_t addr, uint32_t size, int state)
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{
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switch (state & 3) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void
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amd640_write(int func, int addr, uint8_t val, void *priv)
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{
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amd640_t *dev = (amd640_t *) priv;
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/* Read-Only Registers */
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switch(addr){
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case 0x00: case 0x01: case 0x08: case 0x09:
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case 0x0a: case 0x0b: case 0x0c: case 0x0e:
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case 0x0f:
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return;
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}
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switch(addr){
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/* Command */
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case 0x04:
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dev->regs[0x04] = (dev->regs[0x04] & ~0x40) | (val & 0x40);
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/* Status */
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case 0x07:
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dev->regs[0x07] &= ~(val & 0xb0);
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break;
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/* Shadow RAM registers */
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case 0x61:
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if ((dev->regs[0x61] ^ val) & 0x03)
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amd640_map(0xc0000, 0x04000, val & 0x03);
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if ((dev->regs[0x61] ^ val) & 0x0c)
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amd640_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->regs[0x61] ^ val) & 0x30)
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amd640_map(0xc8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->regs[0x61] ^ val) & 0xc0)
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amd640_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
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dev->regs[0x61] = val;
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return;
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case 0x62:
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if ((dev->regs[0x62] ^ val) & 0x03)
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amd640_map(0xd0000, 0x04000, val & 0x03);
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if ((dev->regs[0x62] ^ val) & 0x0c)
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amd640_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
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if ((dev->regs[0x62] ^ val) & 0x30)
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amd640_map(0xd8000, 0x04000, (val & 0x30) >> 4);
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if ((dev->regs[0x62] ^ val) & 0xc0)
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amd640_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
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dev->regs[0x62] = val;
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return;
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case 0x63:
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if ((dev->regs[0x63] ^ val) & 0x30) {
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amd640_map(0xf0000, 0x10000, (val & 0x30) >> 4);
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shadowbios = (((val & 0x30) >> 4) & 0x02);
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}
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if ((dev->regs[0x63] ^ val) & 0xc0)
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amd640_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
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dev->regs[0x63] = val;
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return;
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case 0x65: /* DRAM Control Register #1 */
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dev->regs[0x65] = (dev->regs[0x65] & ~0x20) | (val & 0x20);
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case 0x66: /* DRAM Control Register #2 */
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dev->regs[0x66] = (dev->regs[0x66] & ~0x05) | (val & 0x05);
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case 0x67: /* 32-Bit DRAM Width Control Register */
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dev->regs[0x67] = (dev->regs[0x67] & ~0xc0) | (val & 0xc0);
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case 0x68: /* Reserved (But referenced by the BIOS?) */
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dev->regs[0x68] = (dev->regs[0x68] & ~0x40) | (val & 0x40);
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case 0x6d: /* DRAM Drive Strength Control Register */
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dev->regs[0x6d] = (dev->regs[0x6d] & ~0x6f) | (val & 0x6f);
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case 0x70: /* PCI Buffer Control Register */
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dev->regs[0x70] = (dev->regs[0x70] & ~0x01) | (val & 0x01);
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case 0x71: /* Processor-to-PCI Control Register #1 */
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dev->regs[0x71] = (dev->regs[0x71] & ~0x4e) | (val & 0x4e);
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case 0x73: /* PCI Initiator Control Register #1 */
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dev->regs[0x73] = (dev->regs[0x73] & ~0x0c) | (val & 0x0c);
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case 0x75: /* PCI Arbitration Control Register #1 */
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dev->regs[0x75] = (dev->regs[0x75] & ~0xc7) | (val & 0xc7);
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default:
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dev->regs[addr] = val;
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break;
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}
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}
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static uint8_t
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amd640_read(int func, int addr, void *priv)
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{
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amd640_t *dev = (amd640_t *) priv;
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uint8_t ret = 0xff;
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if(func == 0){
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ret = dev->regs[addr];
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}
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return ret;
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}
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static void
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amd640_reset(void *priv)
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{
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amd640_write(0, 0x63, amd640_read(0, 0x63, priv) & 0xcf, priv);
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}
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static void *
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amd640_init(const device_t *info)
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{
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amd640_t *dev = (amd640_t *) malloc(sizeof(amd640_t));
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pci_add_card(PCI_ADD_NORTHBRIDGE, amd640_read, amd640_write, dev);
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dev->regs[0x00] = 0x06; /* AMD */
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dev->regs[0x01] = 0x11;
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dev->regs[0x02] = 0x95; /* 640 */
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dev->regs[0x03] = 0x15;
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dev->regs[0x04] = 7; /* Command */
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dev->regs[0x06] = 0xa0; /* Status */
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dev->regs[0x07] = 2;
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dev->regs[0x08] = 0x02; /* Revision ID: 0x02 = D, 0x03 = E, 0x04 = F */
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dev->regs[0x0b] = 6; /* Base Class Code */
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dev->regs[0x52] = 2; /* Non-Cacheable control */
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dev->regs[0x58] = 0x40; /* DRAM Configuration register 1 */
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dev->regs[0x59] = 5; /* DRAM Configuration register 2 */
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/* DRAM Bank Endings */
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dev->regs[0x5a] = 1;
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dev->regs[0x5b] = 1;
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dev->regs[0x5c] = 1;
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dev->regs[0x5d] = 1;
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dev->regs[0x5e] = 1;
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dev->regs[0x5f] = 1;
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dev->regs[0x64] = 0xab;
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return dev;
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}
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static void
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amd640_close(void *priv)
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{
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amd640_t *dev = (amd640_t *) priv;
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free(dev);
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}
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const device_t amd640_device = {
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"AMD-640 System Controller",
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DEVICE_PCI,
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0,
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amd640_init,
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amd640_close,
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amd640_reset,
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NULL,
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NULL,
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NULL,
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NULL
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};
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@@ -89,6 +89,9 @@ extern const device_t via_apro_device;
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extern const device_t via_vt82c586b_device;
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extern const device_t via_vt82c596b_device;
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/* AMD */
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extern const device_t amd640_device;
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/* VLSI */
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extern const device_t vlsi_scamp_device;
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@@ -563,7 +563,8 @@ CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \
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intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
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neat.o opti495.o opti5x7.o scamp.o scat.o \
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sis_85c310.o sis_85c471.o sis_85c496.o \
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via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o
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via_apollo.o via_vpx.o via_vt82c586b.o via_vt82c596b.o wd76c10.o \
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amd640.o
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MCHOBJ := machine.o machine_table.o \
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m_xt.o m_xt_compaq.o \
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