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Merge pull request #860 from tiseno100/master

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Restored the Intel 82335 chipset
This commit is contained in:
Miran Grča
2020-06-23 13:53:43 +02:00
committed by GitHub
parent fae3482a1f f29e48d2d7
commit 30bbdcd04c
5 changed files with 202 additions and 139 deletions
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334
src/chipset/i82335.c
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@@ -1,137 +1,197 @@
/* Intel 82335 SX emulation, used by the Phoenix 386 clone. */ /*
* 86Box A hypervisor and IBM PC system emulator that specializes in
#include <stdio.h> * running old operating systems and software designed for IBM
#include <stdint.h> * PC systems and compatibles from 1981 through fairly recent
#include <string.h> * system designs based on the PCI bus.
#include <wchar.h> *
#include <86box/io.h> * This file is part of the 86Box distribution.
#include <86box/mem.h> *
* Implementation of the Intel 82335(KU82335) chipset.
typedef struct *
{ *
uint8_t reg_22; *
uint8_t reg_23; * Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
} i82335_t; * Miran Grca, <mgrca8@gmail.com>
*
i82335_t i82335; * Copyright 2008-2020 Sarah Walker.
* Copyright 2016-2020 Miran Grca.
uint8_t i82335_read(uint16_t addr, void *priv); * Copyright 2020 Tiseno100
*
void i82335_write(uint16_t addr, uint8_t val, void *priv) */
{
int i = 0; #include <stdarg.h>
#include <stdint.h>
int mem_write = 0; #include <stdio.h>
#include <stdlib.h>
// pclog("i82335_write(%04X, %02X)\n", addr, val); #include <string.h>
#include <wchar.h>
switch (addr) #define HAVE_STDARG_H
{ #include <86box/86box.h>
case 0x22: #include "cpu.h"
if ((val ^ i82335.reg_22) & 1) #include <86box/timer.h>
{ #include <86box/io.h>
if (val & 1) #include <86box/device.h>
{ #include <86box/keyboard.h>
for (i = 0; i < 8; i++) #include <86box/mem.h>
{ #include <86box/fdd.h>
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); #include <86box/fdc.h>
shadowbios = 1; #include <86box/chipset.h>
}
}
else typedef struct
{ {
for (i = 0; i < 8; i++) uint8_t reg_22;
{ uint8_t reg_23;
mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); } i82335_t;
shadowbios = 0;
} static uint8_t i82335_read(uint16_t addr, void *priv);
}
static void
flushmmucache(); i82335_write(uint16_t addr, uint8_t val, void *priv)
} {
i82335_t *dev = (i82335_t *) priv;
i82335.reg_22 = val | 0xd8;
break; int mem_write = 0;
case 0x23:
i82335.reg_23 = val; switch (addr)
{
if ((val ^ i82335.reg_22) & 2) case 0x22:
{ if ((val ^ dev->reg_22) & 1)
if (val & 2) {
{ if (val & 1)
for (i = 0; i < 8; i++) {
{ for (int i = 0; i < 8; i++)
mem_set_mem_state(0xc0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); {
shadowbios = 1; mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} shadowbios = 1;
} }
else }
{ else
for (i = 0; i < 8; i++) {
{ for (int i = 0; i < 8; i++)
mem_set_mem_state(0xc0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); {
shadowbios = 0; mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
} shadowbios = 0;
} }
} }
if ((val ^ i82335.reg_22) & 0xc) flushmmucache();
{ }
if (val & 2)
{ dev->reg_22 = val | 0xd8;
for (i = 0; i < 8; i++) break;
{
mem_write = (val & 8) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL; case 0x23:
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | mem_write); dev->reg_23 = val;
shadowbios = 1;
} if ((val ^ dev->reg_22) & 2)
} {
else if (val & 2)
{ {
for (i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
mem_write = (val & 8) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY; mem_set_mem_state(0xc0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | mem_write); shadowbios = 1;
shadowbios = 0; }
} }
} else
} {
for (int i = 0; i < 8; i++)
if ((val ^ i82335.reg_22) & 0xe) {
{ mem_set_mem_state(0xc0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
flushmmucache(); shadowbios = 0;
} }
}
if (val & 0x80) }
{
io_removehandler(0x0022, 0x0001, i82335_read, NULL, NULL, i82335_write, NULL, NULL, NULL); if ((val ^ dev->reg_22) & 0xc)
} {
break; if (val & 2)
} {
} for (int i = 0; i < 8; i++)
{
uint8_t i82335_read(uint16_t addr, void *priv) mem_write = (val & 8) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL;
{ mem_set_mem_state(0xa0000, 0x20000, MEM_READ_INTERNAL | mem_write);
// pclog("i82335_read(%04X)\n", addr); shadowbios = 1;
if (addr == 0x22) }
{ }
return i82335.reg_22; else
} {
else if (addr == 0x23) for (int i = 0; i < 8; i++)
{ {
return i82335.reg_23; mem_write = (val & 8) ? MEM_WRITE_DISABLED : MEM_WRITE_EXTANY;
} mem_set_mem_state(0xa0000, 0x20000, MEM_READ_EXTANY | mem_write);
else shadowbios = 0;
{ }
return 0; }
} }
}
if ((val ^ dev->reg_22) & 0xe)
void i82335_init() {
{ flushmmucache();
memset(&i82335, 0, sizeof(i82335_t)); }
i82335.reg_22 = 0xd8; if (val & 0x80)
{
io_sethandler(0x0022, 0x0014, i82335_read, NULL, NULL, i82335_write, NULL, NULL, NULL); io_removehandler(0x0022, 0x0001, i82335_read, NULL, NULL, i82335_write, NULL, NULL, NULL);
} io_removehandler(0x0023, 0x0001, i82335_read, NULL, NULL, i82335_write, NULL, NULL, NULL);
}
break;
}
}
static uint8_t
i82335_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
i82335_t *dev = (i82335_t *) priv;
switch(addr){
case 0x22:
return dev->reg_22;
break;
case 0x23:
return dev->reg_23;
break;
default:
return 0;
break;
}
return ret;
}
static void
i82335_close(void *priv)
{
i82335_t *dev = (i82335_t *) priv;
free(dev);
}
static void *
i82335_init(const device_t *info)
{
i82335_t *dev = (i82335_t *) malloc(sizeof(i82335_t));
memset(dev, 0, sizeof(i82335_t));
dev->reg_22 = 0xd8;
io_sethandler(0x0022, 0x0001, i82335_read, NULL, NULL, i82335_write, NULL, NULL, dev);
io_sethandler(0x0023, 0x0001, i82335_read, NULL, NULL, i82335_write, NULL, NULL, dev);
return dev;
}
const device_t i82335_device = {
"Intel 82335",
0,
0,
i82335_init, i82335_close, NULL,
NULL, NULL, NULL,
NULL
};

3
src/include/86box/chipset.h
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@@ -31,7 +31,8 @@ extern const device_t ali1429_device;
extern const device_t headland_device; extern const device_t headland_device;
extern const device_t headland_386_device; extern const device_t headland_386_device;
/* Intel 4x0xX */ /* Intel */
extern const device_t i82335_device;
extern const device_t i420ex_device; extern const device_t i420ex_device;
extern const device_t i420tx_device; extern const device_t i420tx_device;
extern const device_t i420zx_device; extern const device_t i420zx_device;

1
src/include/86box/machine.h
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@@ -235,6 +235,7 @@ extern int machine_at_spc4216p_init(const machine_t *);
extern int machine_at_kmxc02_init(const machine_t *); extern int machine_at_kmxc02_init(const machine_t *);
extern int machine_at_deskmaster286_init(const machine_t *); extern int machine_at_deskmaster286_init(const machine_t *);
extern int machine_at_shuttle386sx_init(const machine_t *);
extern int machine_at_commodore_sl386sx_init(const machine_t *); extern int machine_at_commodore_sl386sx_init(const machine_t *);
extern int machine_at_wd76c10_init(const machine_t *); extern int machine_at_wd76c10_init(const machine_t *);

1
src/machine/machine_table.c
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@@ -171,6 +171,7 @@ const machine_t machines[] = {
{ "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL }, { "[NEAT] DTK 386SX clone", "dtk386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_neat_init, NULL },
{ "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL }, { "[NEAT] Goldstar 386", "goldstar386", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512, 8192, 128, 127, machine_at_goldstar386_init, NULL },
{ "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL }, { "[SCAT] KMX-C-02", "kmxc02", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_kmxc02_init, NULL },
{ "[Intel 82335] Shuttle 386SX", "shuttle386sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512, 8192, 128, 127, machine_at_shuttle386sx_init, NULL },
/* 386SX machines which utilize the MCA bus */ /* 386SX machines which utilize the MCA bus */
{ "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL }, { "[MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", MACHINE_TYPE_386SX, {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL },

2
src/win/Makefile.mingw
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@@ -559,7 +559,7 @@ CPUOBJ := cpu.o cpu_table.o \
x86seg.o x87.o x87_timings.o \ x86seg.o x87.o x87_timings.o \
$(DYNARECOBJ) $(DYNARECOBJ)
CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o i82335.o\
intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \ intel_420ex.o intel_4x0.o intel_sio.o intel_piix.o ioapic.o \
neat.o opti495.o opti5x7.o scamp.o scat.o \ neat.o opti495.o opti5x7.o scamp.o scat.o \
sis_85c310.o sis_85c471.o sis_85c496.o \ sis_85c310.o sis_85c471.o sis_85c496.o \