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Added a PC Partner MB500N specific workaround to the i4x0 cache control register write.

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OBattler
2024-05-08 23:44:43 +02:00
parent b159cd5b12
commit 4fe7ee9675
1 changed files with 4 additions and 1 deletions
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5
src/chipset/intel_4x0.c
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@@ -518,7 +518,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430FX:
case INTEL_430VX:
case INTEL_430TX:
regs[0x52] = (regs[0x52] & 0xf0) | (val & 0x0b);
if (!strcmp(machine_get_internal_name(), "mb500n"))
regs[0x52] = val;
else
regs[0x52] = (regs[0x52] & 0xf4) | (val & 0x0b);
cpu_cache_ext_enabled = ((val & 0x03) == 0x01);
cpu_update_waitstates();
break;