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PCI Reset Control register now forces bit 4 to be written as 0, fixes resets through this register from the second soft reset onwards.

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OBattler
2019-11-08 08:06:02 +01:00
parent 9c8c9361a6
commit 56a8da6cf5
1 changed files with 2 additions and 2 deletions
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4
src/pci.c
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@@ -8,7 +8,7 @@
*
* Implementation the PCI bus.
*
* Version: @(#)pci.c 1.0.3 2019/10/30
* Version: @(#)pci.c 1.0.4 2019/11/06
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -635,7 +635,7 @@ trc_write(uint16_t port, uint8_t val, void *priv)
if (!(trc_reg & 4) && (val & 4))
trc_reset(val);
trc_reg = val & 0xfd;
trc_reg = val & 0xfb;
}