80486DX2-66/86Box-fork
1
0
Fork 0
Code Issues Pull Requests Activity

PCI Reset Control register now forces bit 4 to be written as 0, fixes resets through this register from the second soft reset onwards.

Browse Source
This commit is contained in:
OBattler
2019-11-08 08:06:02 +01:00
parent 9c8c9361a6
commit 56a8da6cf5
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/pci.c
View File

@@ -8,7 +8,7 @@
* *
* Implementation the PCI bus. * Implementation the PCI bus.
* *
* Version: @(#)pci.c 1.0.3 2019/10/30 * Version: @(#)pci.c 1.0.4 2019/11/06
* *
* Authors: Miran Grca, <mgrca8@gmail.com> * Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com> * Fred N. van Kempen, <decwiz@yahoo.com>
@@ -635,7 +635,7 @@ trc_write(uint16_t port, uint8_t val, void *priv)
if (!(trc_reg & 4) && (val & 4)) if (!(trc_reg & 4) && (val & 4))
trc_reset(val); trc_reset(val);
trc_reg = val & 0xfd; trc_reg = val & 0xfb;
} }