Named-initializers for 80386SX CPU's
This commit is contained in:
@@ -1009,12 +1009,92 @@ const cpu_family_t cpu_families[] = {
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.name = "i386SX",
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.internal_name = "i386sx",
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.cpus = (const CPU[]) {
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{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386SX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386SX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386SX,
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@@ -1022,12 +1102,92 @@ const cpu_family_t cpu_families[] = {
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.name = "Am386SX",
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.internal_name = "am386sx",
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.cpus = (const CPU[]) {
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{"16", CPU_386SX, fpus_80386, 16000000, 1, 5000, 0x2308, 0, 0, 0, 3,3,3,3, 2},
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{"20", CPU_386SX, fpus_80386, 20000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"25", CPU_386SX, fpus_80386, 25000000, 1, 5000, 0x2308, 0, 0, 0, 4,4,3,3, 3},
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{"33", CPU_386SX, fpus_80386, 33333333, 1, 5000, 0x2308, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386SX, fpus_80386, 40000000, 1, 5000, 0x2308, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "16",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 16000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 3,
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.mem_write_cycles = 3,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 2
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},
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{
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.name = "20",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 20000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "25",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 25000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 4,
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.mem_write_cycles = 4,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 3
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},
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{
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.name = "33",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386SX,
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.fpus = fpus_80386,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2308,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386DX,
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@@ -1081,9 +1241,41 @@ const cpu_family_t cpu_families[] = {
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.name = "M6117",
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.internal_name = "m6117",
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.cpus = (const CPU[]) { /* All timings and edx_reset values assumed. */
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{"33", CPU_386SX, fpus_none, 33333333, 1, 5000, 0x2309, 0, 0, 0, 6,6,3,3, 4},
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{"40", CPU_386SX, fpus_none, 40000000, 1, 5000, 0x2309, 0, 0, 0, 7,7,3,3, 5},
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{"", 0}
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{
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.name = "33",
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.cpu_type = CPU_386SX,
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.fpus = fpus_none,
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.rspeed = 33333333,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2309,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 6,
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.mem_write_cycles = 6,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 4
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},
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{
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.name = "40",
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.cpu_type = CPU_386SX,
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.fpus = fpus_none,
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.rspeed = 40000000,
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.multi = 1,
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.voltage = 5000,
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.edx_reset = 0x2309,
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.cpuid_model = 0,
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.cyrix_id = 0,
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.cpu_flags = 0,
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.mem_read_cycles = 7,
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.mem_write_cycles = 7,
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.cache_read_cycles = 3,
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.cache_write_cycles = 3,
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.atclk_div = 5
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},
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{ .name = "", 0 }
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}
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}, {
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.package = CPU_PKG_386SLC_IBM,
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