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Add ISA speed control to PIIX and VIA southbridges, and M6117 SoC

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This commit is contained in:
RichardG867
2021-03-14 19:44:09 -03:00
parent 0f80e956d5
commit 7cdceb056f
3 changed files with 91 additions and 2 deletions
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38
src/chipset/ali6117.c
View File

@@ -146,6 +146,42 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x1e:
val &= 0x07;
switch (val) {
/* Half PIT clock. */
case 0x0:
cpu_set_isa_speed(7159091);
break;
/* Divisors on the input clock PCLK2, which is double the CPU clock. */
case 0x1:
cpu_set_isa_speed(cpu_busspeed / 1.5);
break;
case 0x2:
cpu_set_isa_speed(cpu_busspeed / 2);
break;
case 0x3:
cpu_set_isa_speed(cpu_busspeed / 2.5);
break;
case 0x4:
cpu_set_isa_speed(cpu_busspeed / 3);
break;
case 0x5:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 0x6:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
case 0x7:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
}
break;
case 0x20:
@@ -282,6 +318,8 @@ ali6117_reset(void *priv)
dev->regs[0x34] = 0x04; /* enable internal RTC */
dev->regs[0x35] = 0x20; /* enable internal KBC */
dev->regs[0x36] = dev->local & 0x4; /* M6117D ID */
cpu_set_isa_speed(7159091);
}

7
src/chipset/intel_piix.c
View File

@@ -1237,9 +1237,10 @@ static void
piix_speed_changed(void *priv)
{
piix_t *dev = (piix_t *) priv;
int te;
if (!dev)
return;
te = timer_is_enabled(&dev->fast_off_timer);
int te = timer_is_enabled(&dev->fast_off_timer);
timer_stop(&dev->fast_off_timer);
if (te)
@@ -1306,6 +1307,8 @@ static void
dev->port_92 = device_add(&port_92_pci_device);
cpu_set_isa_pci_div(4);
dma_alias_set();
if (dev->type < 4)

48
src/chipset/via_pipc.c
View File

@@ -503,6 +503,52 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
dev->pci_isa_regs[0x07] &= ~(val & 0xb0);
break;
case 0x42:
dev->pci_isa_regs[0x42] = val & 0xcf;
switch (val & 0xf) {
/* Divisors on the PCI clock. */
case 0x8:
cpu_set_isa_pci_div(3);
break;
case 0x9:
cpu_set_isa_pci_div(2);
break;
case 0xa:
cpu_set_isa_pci_div(4);
break;
case 0xb:
cpu_set_isa_pci_div(6);
break;
case 0xc:
cpu_set_isa_pci_div(5);
break;
case 0xd:
cpu_set_isa_pci_div(10);
break;
case 0xe:
cpu_set_isa_pci_div(12);
break;
/* Half PIT clock. */
case 0xf:
cpu_set_isa_speed(7159091);
break;
/* Divisor 4 on the PCI clock whenever bit 3 is clear. */
default:
cpu_set_isa_pci_div(4);
break;
}
break;
case 0x47:
if (val & 0x01)
trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL);
@@ -940,6 +986,8 @@ pipc_init(const device_t *info)
device_add(&port_92_pci_device);
cpu_set_isa_pci_div(4);
dma_alias_set();
if (dev->local <= VIA_PIPC_586B) {