Sanitize some old chipset code (Part 3)
Fixed the Indentation of the Intel 82335, removed useless includes and numerous bugfixes on the OPTi Python.
This commit is contained in:
@@ -8,7 +8,7 @@
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*
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* Implementation of the Intel 82335(KU82335) chipset.
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*
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* Copyright 2020 Tiseno100
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* Copyright 2021 Tiseno100
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*
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*/
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@@ -24,10 +24,7 @@
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/chipset.h>
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/* Shadow capabilities */
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@@ -38,7 +35,7 @@
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/* Granularity Register Enable & Recalc */
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#define EXTENDED_GRANULARITY_ENABLED (dev->regs[0x2c] & 0x01)
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#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i+8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW)
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#define GRANULARITY_RECALC ((dev->regs[0x2e] & (1 << (i + 8))) ? ((dev->regs[0x2e] & (1 << i)) ? RO_SHADOW : RW_SHADOW) : DISABLED_SHADOW)
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/* R/W operator for the Video RAM region */
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#define DETERMINE_VIDEO_RAM_WRITE_ACCESS ((dev->regs[0x22] & (0x08 << 8)) ? RW_SHADOW : RO_SHADOW)
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@@ -61,8 +58,8 @@ typedef struct
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{
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uint16_t regs[256],
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cfg_locked;
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cfg_locked;
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} intel_82335_t;
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@@ -73,10 +70,11 @@ intel_82335_log(const char *fmt, ...)
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{
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va_list ap;
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if (intel_82335_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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if (intel_82335_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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@@ -86,92 +84,90 @@ intel_82335_log(const char *fmt, ...)
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static void
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intel_82335_write(uint16_t addr, uint16_t val, void *priv)
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{
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intel_82335_t *dev = (intel_82335_t *) priv;
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intel_82335_t *dev = (intel_82335_t *)priv;
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uint32_t romsize = 0, base = 0, i = 0, rc1_remap = 0, rc2_remap = 0;
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dev->regs[addr] = val;
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if(!dev->cfg_locked)
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if (!dev->cfg_locked)
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{
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intel_82335_log("Register %02x: Write %04x\n", addr, val);
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intel_82335_log("Register %02x: Write %04x\n", addr, val);
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switch (addr) {
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case 0x22: /* Memory Controller */
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switch (addr)
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{
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case 0x22: /* Memory Controller */
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/* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */
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romsize = ROM_SIZE;
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/* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */
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romsize = ROM_SIZE;
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if (!EXTENDED_GRANULARITY_ENABLED)
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{
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shadowbios = !!(dev->regs[0x22] & 0x01);
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shadowbios_write = !!(dev->regs[0x22] & 0x01);
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if (!EXTENDED_GRANULARITY_ENABLED)
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{
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shadowbios = !!(dev->regs[0x22] & 0x01);
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shadowbios_write = !!(dev->regs[0x22] & 0x01);
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/* Base System 512/640KB set */
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mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
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/* Base System 512/640KB set */
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mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
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/* Video RAM shadow*/
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mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW);
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/* Video RAM shadow*/
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mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW);
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/* Option ROM shadow */
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mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW);
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/* Option ROM shadow */
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mem_set_mem_state_both(0xc0000, 0x20000, (dev->regs[0x22] & (0x02 << 8)) ? ENABLED_SHADOW : DISABLED_SHADOW);
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/* System ROM shadow */
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mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW);
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}
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break;
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/* System ROM shadow */
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mem_set_mem_state_both(0xe0000, 0x20000, (dev->regs[0x22] & 0x01) ? ENABLED_SHADOW : DISABLED_SHADOW);
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}
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break;
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case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */
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case 0x26:
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rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0;
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rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0;
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mem_remap_top(rc1_remap+rc2_remap);
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break;
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case 0x24: /* Roll Compare (Just top remapping. Not followed according to datasheet!) */
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case 0x26:
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rc1_remap = (dev->regs[0x24] & 0x01) ? DEFINE_RC1_REMAP_SIZE : 0;
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rc2_remap = (dev->regs[0x26] & 0x01) ? DEFINE_RC2_REMAP_SIZE : 0;
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mem_remap_top(rc1_remap + rc2_remap);
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break;
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case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */
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if(EXTENDED_GRANULARITY_ENABLED)
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{
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for(i=0; i<8; i++)
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{
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base = 0xc0000 + (i << 15);
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shadowbios = (dev->regs[0x2e] & (1 << (i+8))) && (base == romsize);
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shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize);
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mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC);
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}
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break;
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}
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}
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case 0x2e: /* Extended Granularity (Enabled if Bit 0 in Register 2Ch is set) */
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if (EXTENDED_GRANULARITY_ENABLED)
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{
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for (i = 0; i < 8; i++)
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{
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base = 0xc0000 + (i << 15);
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shadowbios = (dev->regs[0x2e] & (1 << (i + 8))) && (base == romsize);
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shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize);
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mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC);
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}
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break;
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}
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}
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}
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/* Unlock/Lock configuration registers */
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dev->cfg_locked = LOCK_STATUS;
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}
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static uint16_t
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intel_82335_read(uint16_t addr, void *priv)
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{
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intel_82335_t *dev = (intel_82335_t *) priv;
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intel_82335_t *dev = (intel_82335_t *)priv;
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intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]);
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return dev->regs[addr];
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}
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static void
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intel_82335_close(void *priv)
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{
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intel_82335_t *dev = (intel_82335_t *) priv;
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intel_82335_t *dev = (intel_82335_t *)priv;
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free(dev);
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}
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static void *
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intel_82335_init(const device_t *info)
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{
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intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t));
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intel_82335_t *dev = (intel_82335_t *)malloc(sizeof(intel_82335_t));
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memset(dev, 0, sizeof(intel_82335_t));
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memset(dev->regs, 0, sizeof(dev->regs));
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@@ -195,17 +191,19 @@ intel_82335_init(const device_t *info)
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io_sethandler(0x002c, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
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/* Extended Granularity */
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io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
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io_sethandler(0x002e, 0x0001, NULL, intel_82335_read, NULL, NULL, intel_82335_write, NULL, dev);
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return dev;
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}
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const device_t intel_82335_device = {
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"Intel 82335",
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0,
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0,
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intel_82335_init, intel_82335_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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intel_82335_init,
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intel_82335_close,
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NULL,
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{NULL},
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NULL,
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NULL,
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NULL};
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@@ -6,13 +6,15 @@
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the OPTi 82C546/82C547 & 82C596/82C597 chipsets.
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* Implementation of the OPTi 82C546/82C547(Python) & 82C596/82C597(Cobra) chipsets.
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* Authors: plant/nerd73
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* Miran Grca, <mgrca8@gmail.com>
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* Authors: plant/nerd73,
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* Miran Grca, <mgrca8@gmail.com>
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* Tiseno100
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*
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* Copyright 2020 plant/nerd73.
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* Copyright 2020 Miran Grca.
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* Copyright 2020 plant/nerd73.
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* Copyright 2020 Miran Grca.
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* Copyright 2021 Tiseno100.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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@@ -26,142 +28,134 @@
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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/* Shadow RAM */
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#define SHADOW_RECALC (((dev->regs[(i < 4) ? 4 : 5] & (1 << ((i < 4) ? i : i - 4) * 2)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[(i < 4) ? 4 : 5] & (1 << (((i < 4) ? i : i - 4) * 2 + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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#define SHADOW_E_RECALC (((dev->regs[0x06] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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#define SHADOW_F_RECALC (((dev->regs[0x06] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
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typedef struct
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{
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uint8_t idx,
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regs[16];
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port_92_t *port_92;
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uint8_t idx, regs[16];
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} opti5x7_t;
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#ifdef ENABLE_OPTI5X7_LOG
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int opti5x7_do_log = ENABLE_OPTI5X7_LOG;
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static void
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opti5x7_log(const char *fmt, ...)
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{
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va_list ap;
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if (opti5x7_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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if (opti5x7_do_log)
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{
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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#define opti5x7_log(fmt, ...)
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#endif
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static void
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opti5x7_recalc(opti5x7_t *dev)
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shadow_map(opti5x7_t *dev)
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{
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uint32_t base;
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uint32_t i, shflags = 0;
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uint32_t reg, lowest_bit;
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shadowbios = 0;
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shadowbios_write = 0;
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for (i = 0; i < 8; i++) {
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base = 0xc0000 + (i << 14);
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lowest_bit = (i << 1) & 0x07;
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reg = 0x04 + ((base >> 16) & 0x01);
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shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(base, 0x4000, shflags);
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}
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shadowbios |= !!(dev->regs[0x06] & 0x05);
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shadowbios_write |= !!(dev->regs[0x06] & 0x0a);
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shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xe0000, 0x10000, shflags);
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shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
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shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
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mem_set_mem_state(0xf0000, 0x10000, shflags);
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for (int i = 0; i < 8; i++)
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mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, SHADOW_RECALC);
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mem_set_mem_state_both(0xe0000, 0x10000, SHADOW_E_RECALC);
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shadowbios = !!(dev->regs[0x06] & 5);
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shadowbios_write = !!(dev->regs[0x06] & 0x0a);
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mem_set_mem_state_both(0xf0000, 0x10000, SHADOW_F_RECALC);
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flushmmucache();
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}
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static void
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opti5x7_write(uint16_t addr, uint8_t val, void *priv)
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{
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opti5x7_t *dev = (opti5x7_t *) priv;
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opti5x7_log("Write %02x to OPTi 5x7 address %02x\n", val, addr);
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switch (addr) {
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case 0x22:
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dev->idx = val;
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break;
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case 0x24:
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dev->regs[dev->idx] = val;
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switch(dev->idx) {
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case 0x02:
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08);
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break;
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{
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opti5x7_t *dev = (opti5x7_t *)priv;
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case 0x04:
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case 0x05:
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case 0x06:
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opti5x7_recalc(dev);
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break;
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}
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break;
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switch (addr)
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{
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case 0x22:
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dev->idx = val;
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break;
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case 0x24:
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opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, val);
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switch (dev->idx)
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{
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case 0x00: /* DRAM Configuration Register #1 */
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dev->regs[dev->idx] = val & 0x7f;
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break;
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case 0x01: /* DRAM Control Register #1 */
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dev->regs[dev->idx] = val;
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break;
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case 0x02: /* Cache Control Register #1 */
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dev->regs[dev->idx] = val;
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cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c);
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cpu_update_waitstates();
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break;
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case 0x03: /* Cache Control Register #2 */
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dev->regs[dev->idx] = val;
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break;
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case 0x04: /* Shadow RAM Control Register #1 */
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case 0x05: /* Shadow RAM Control Register #2 */
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case 0x06: /* Shadow RAM Control Register #3 */
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dev->regs[dev->idx] = val;
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shadow_map(dev);
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break;
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case 0x07: /* Tag Test Register */
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case 0x08: /* CPU Cache Control Register #1 */
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case 0x09: /* System Memory Function Register #1 */
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case 0x0a: /* System Memory Address Decode Register #1 */
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case 0x0b: /* System Memory Address Decode Register #2 */
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dev->regs[dev->idx] = val;
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break;
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case 0x0c: /* Extended DMA Register */
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dev->regs[dev->idx] = val & 0xcf;
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break;
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case 0x0d: /* ROMCS# Register */
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case 0x0e: /* Local Master Preemption Register */
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case 0x0f: /* Deturbo Control Register #1 */
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case 0x10: /* Cache Write-Hit Control Register */
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case 0x11: /* Master Cycle Control Register */
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dev->regs[dev->idx] = val;
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break;
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}
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break;
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}
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}
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static uint8_t
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opti5x7_read(uint16_t addr, void *priv)
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{
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uint8_t ret = 0xff;
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opti5x7_t *dev = (opti5x7_t *) priv;
|
||||
opti5x7_t *dev = (opti5x7_t *)priv;
|
||||
|
||||
switch (addr) {
|
||||
case 0x24:
|
||||
opti5x7_log("Read from OPTi 5x7 register %02x\n", dev->idx);
|
||||
ret = dev->regs[dev->idx];
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
return (addr == 0x24) ? dev->regs[dev->idx] : 0xff;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
opti5x7_close(void *priv)
|
||||
{
|
||||
opti5x7_t *dev = (opti5x7_t *) priv;
|
||||
opti5x7_t *dev = (opti5x7_t *)priv;
|
||||
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
opti5x7_init(const device_t *info)
|
||||
{
|
||||
opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t));
|
||||
opti5x7_t *dev = (opti5x7_t *)malloc(sizeof(opti5x7_t));
|
||||
memset(dev, 0, sizeof(opti5x7_t));
|
||||
|
||||
io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
|
||||
io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
|
||||
|
||||
dev->port_92 = device_add(&port_92_device);
|
||||
device_add(&port_92_device);
|
||||
|
||||
return dev;
|
||||
}
|
||||
@@ -170,7 +164,10 @@ const device_t opti5x7_device = {
|
||||
"OPTi 82C5x6/82C5x7",
|
||||
0,
|
||||
0,
|
||||
opti5x7_init, opti5x7_close, NULL,
|
||||
{ NULL }, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
opti5x7_init,
|
||||
opti5x7_close,
|
||||
NULL,
|
||||
{NULL},
|
||||
NULL,
|
||||
NULL,
|
||||
NULL};
|
||||
|
Reference in New Issue
Block a user