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Sanitize some old chipset code (Part 3)

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Fixed the Indentation of the Intel 82335, removed useless includes and numerous bugfixes on the OPTi Python.
This commit is contained in:
Panagiotis
2021-02-13 12:31:04 +02:00
committed by GitHub
parent e3fc96738a
commit 8b7d643452
2 changed files with 148 additions and 153 deletions
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26
src/chipset/intel_82335.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Intel 82335(KU82335) chipset.
*
* Copyright 2020 Tiseno100
* Copyright 2021 Tiseno100
*
*/
@@ -24,10 +24,7 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
/* Shadow capabilities */
@@ -73,7 +70,8 @@ intel_82335_log(const char *fmt, ...)
{
va_list ap;
if (intel_82335_do_log) {
if (intel_82335_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
@@ -96,7 +94,8 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
intel_82335_log("Register %02x: Write %04x\n", addr, val);
switch (addr) {
switch (addr)
{
case 0x22: /* Memory Controller */
/* Check if the ROM chips are 256 or 512Kbit (Just for Shadowing sanity) */
@@ -147,7 +146,6 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
dev->cfg_locked = LOCK_STATUS;
}
static uint16_t
intel_82335_read(uint16_t addr, void *priv)
{
@@ -156,7 +154,6 @@ intel_82335_read(uint16_t addr, void *priv)
intel_82335_log("Register %02x: Read %04x\n", addr, dev->regs[addr]);
return dev->regs[addr];
}
static void
@@ -167,7 +164,6 @@ intel_82335_close(void *priv)
free(dev);
}
static void *
intel_82335_init(const device_t *info)
{
@@ -200,12 +196,14 @@ intel_82335_init(const device_t *info)
return dev;
}
const device_t intel_82335_device = {
"Intel 82335",
0,
0,
intel_82335_init, intel_82335_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
intel_82335_init,
intel_82335_close,
NULL,
{NULL},
NULL,
NULL,
NULL};

135
src/chipset/opti5x7.c
View File

@@ -6,13 +6,15 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C546/82C547 & 82C596/82C597 chipsets.
* Implementation of the OPTi 82C546/82C547(Python) & 82C596/82C597(Cobra) chipsets.
* Authors: plant/nerd73
* Authors: plant/nerd73,
* Miran Grca, <mgrca8@gmail.com>
* Tiseno100
*
* Copyright 2020 plant/nerd73.
* Copyright 2020 Miran Grca.
* Copyright 2021 Tiseno100.
*/
#include <stdarg.h>
#include <stdint.h>
@@ -26,32 +28,30 @@
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
/* Shadow RAM */
#define SHADOW_RECALC (((dev->regs[(i < 4) ? 4 : 5] & (1 << ((i < 4) ? i : i - 4) * 2)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[(i < 4) ? 4 : 5] & (1 << (((i < 4) ? i : i - 4) * 2 + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
#define SHADOW_E_RECALC (((dev->regs[0x06] & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 2) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
#define SHADOW_F_RECALC (((dev->regs[0x06] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[0x06] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY))
typedef struct
{
uint8_t idx,
regs[16];
port_92_t *port_92;
uint8_t idx, regs[16];
} opti5x7_t;
#ifdef ENABLE_OPTI5X7_LOG
int opti5x7_do_log = ENABLE_OPTI5X7_LOG;
static void
opti5x7_log(const char *fmt, ...)
{
va_list ap;
if (opti5x7_do_log) {
if (opti5x7_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
@@ -61,88 +61,83 @@ opti5x7_log(const char *fmt, ...)
#define opti5x7_log(fmt, ...)
#endif
static void
opti5x7_recalc(opti5x7_t *dev)
shadow_map(opti5x7_t *dev)
{
uint32_t base;
uint32_t i, shflags = 0;
uint32_t reg, lowest_bit;
shadowbios = 0;
shadowbios_write = 0;
for (i = 0; i < 8; i++) {
base = 0xc0000 + (i << 14);
lowest_bit = (i << 1) & 0x07;
reg = 0x04 + ((base >> 16) & 0x01);
shflags = (dev->regs[reg] & (1 << lowest_bit)) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[reg] & (1 << (lowest_bit + 1))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(base, 0x4000, shflags);
}
shadowbios |= !!(dev->regs[0x06] & 0x05);
shadowbios_write |= !!(dev->regs[0x06] & 0x0a);
shflags = (dev->regs[0x06] & 0x01) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x02) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xe0000, 0x10000, shflags);
shflags = (dev->regs[0x06] & 0x04) ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
shflags |= (dev->regs[0x06] & 0x08) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
mem_set_mem_state(0xf0000, 0x10000, shflags);
for (int i = 0; i < 8; i++)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, SHADOW_RECALC);
mem_set_mem_state_both(0xe0000, 0x10000, SHADOW_E_RECALC);
shadowbios = !!(dev->regs[0x06] & 5);
shadowbios_write = !!(dev->regs[0x06] & 0x0a);
mem_set_mem_state_both(0xf0000, 0x10000, SHADOW_F_RECALC);
flushmmucache();
}
static void
opti5x7_write(uint16_t addr, uint8_t val, void *priv)
{
opti5x7_t *dev = (opti5x7_t *)priv;
opti5x7_log("Write %02x to OPTi 5x7 address %02x\n", val, addr);
switch (addr) {
switch (addr)
{
case 0x22:
dev->idx = val;
break;
case 0x24:
opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, val);
switch (dev->idx)
{
case 0x00: /* DRAM Configuration Register #1 */
dev->regs[dev->idx] = val & 0x7f;
break;
case 0x01: /* DRAM Control Register #1 */
dev->regs[dev->idx] = val;
switch(dev->idx) {
case 0x02:
cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x04 & 0x08);
break;
case 0x04:
case 0x05:
case 0x06:
opti5x7_recalc(dev);
case 0x02: /* Cache Control Register #1 */
dev->regs[dev->idx] = val;
cpu_cache_ext_enabled = !!(dev->regs[0x02] & 0x0c);
cpu_update_waitstates();
break;
case 0x03: /* Cache Control Register #2 */
dev->regs[dev->idx] = val;
break;
case 0x04: /* Shadow RAM Control Register #1 */
case 0x05: /* Shadow RAM Control Register #2 */
case 0x06: /* Shadow RAM Control Register #3 */
dev->regs[dev->idx] = val;
shadow_map(dev);
break;
case 0x07: /* Tag Test Register */
case 0x08: /* CPU Cache Control Register #1 */
case 0x09: /* System Memory Function Register #1 */
case 0x0a: /* System Memory Address Decode Register #1 */
case 0x0b: /* System Memory Address Decode Register #2 */
dev->regs[dev->idx] = val;
break;
case 0x0c: /* Extended DMA Register */
dev->regs[dev->idx] = val & 0xcf;
break;
case 0x0d: /* ROMCS# Register */
case 0x0e: /* Local Master Preemption Register */
case 0x0f: /* Deturbo Control Register #1 */
case 0x10: /* Cache Write-Hit Control Register */
case 0x11: /* Master Cycle Control Register */
dev->regs[dev->idx] = val;
break;
}
break;
}
}
static uint8_t
opti5x7_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
opti5x7_t *dev = (opti5x7_t *)priv;
switch (addr) {
case 0x24:
opti5x7_log("Read from OPTi 5x7 register %02x\n", dev->idx);
ret = dev->regs[dev->idx];
break;
return (addr == 0x24) ? dev->regs[dev->idx] : 0xff;
}
return ret;
}
static void
opti5x7_close(void *priv)
{
@@ -151,7 +146,6 @@ opti5x7_close(void *priv)
free(dev);
}
static void *
opti5x7_init(const device_t *info)
{
@@ -161,7 +155,7 @@ opti5x7_init(const device_t *info)
io_sethandler(0x0022, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti5x7_read, NULL, NULL, opti5x7_write, NULL, NULL, dev);
dev->port_92 = device_add(&port_92_device);
device_add(&port_92_device);
return dev;
}
@@ -170,7 +164,10 @@ const device_t opti5x7_device = {
"OPTi 82C5x6/82C5x7",
0,
0,
opti5x7_init, opti5x7_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
opti5x7_init,
opti5x7_close,
NULL,
{NULL},
NULL,
NULL,
NULL};