FDC: Disable DSR reset on the PS/1-2011/2121 / PS/2-30 FDC.
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@@ -780,24 +780,26 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
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}
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return;
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case 4:
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if (!(val & 0x80)) {
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timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
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fdc->interrupt = -6;
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}
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if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) {
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if (fdc->power_down) {
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timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC);
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fdc->interrupt = -5;
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} else {
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if (!(fdc->flags & FDC_FLAG_PS1)) {
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if (!(val & 0x80)) {
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timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
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fdc->interrupt = -1;
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fdc->interrupt = -6;
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}
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if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) {
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if (fdc->power_down) {
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timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC);
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fdc->interrupt = -5;
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} else {
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timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
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fdc->interrupt = -1;
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fdc->perp &= 0xfc;
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fdc->perp &= 0xfc;
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for (i = 0; i < FDD_NUM; i++)
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ui_sb_update_icon(SB_FLOPPY | i, 0);
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for (i = 0; i < FDD_NUM; i++)
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ui_sb_update_icon(SB_FLOPPY | i, 0);
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fdc_ctrl_reset(fdc);
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fdc_ctrl_reset(fdc);
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}
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}
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}
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fdc->dsr = val;
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