Miran Grča
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8ebcfe766e
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Merge pull request #883 from amdk6/master
Added various Dell machines
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2020-06-30 15:56:41 +02:00 |
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Miran Grča
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56098700d1
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Merge pull request #882 from nerd73/pythonfix
Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
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2020-06-30 15:56:29 +02:00 |
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OBattler
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602cadf863
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Removed the fdc_at_device adding from the PS/1 Model 2133, as the FDC is now correctly added by the Super I/O chip.
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2020-06-30 15:52:47 +02:00 |
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OBattler
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33a0cf53c4
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Removed the "PS/1 Model 2133" Super I/O chip as it has been identified as a National Semiconductors PC87332 on a different set of ports, the PS/1 Model 2133 now uses that.
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2020-06-30 15:49:47 +02:00 |
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OBattler
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81d178e9f6
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Rewrote the VLSI 82C480 chipset emuluation and gave the PS/1 Model 2133 its Super I/O chip.
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2020-06-30 15:37:07 +02:00 |
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Gey Cunt
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57d7982a53
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Added various Dell machines
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2020-06-30 16:15:48 +03:00 |
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nerd73
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546f0a83e7
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Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
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2020-06-29 22:06:27 -06:00 |
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OBattler
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13e8d9c923
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Fixed Shadow RAM handling for all OPTi 486 chipsets.
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2020-06-30 03:24:06 +02:00 |
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OBattler
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9402f98a3b
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Rewrote the OPTi 82C495 emulation, added the OPTi 82C493, did some changes to the 82C8xx, and updated Makefile.local.
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2020-06-30 00:34:49 +02:00 |
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OBattler
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a4301708da
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Added the OPTi 802G device (the 802G and 895 are register-identical), and added port 23h to the OPTi 8xx'es.
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2020-06-29 18:44:20 +02:00 |
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OBattler
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4a8aa601b6
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Fixed (and improved) the OPTi 895 chipset implementation.
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2020-06-29 18:13:14 +02:00 |
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Miran Grča
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e4954193c8
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Merge pull request #881 from tiseno100/master
Implemented the OPTi 82C895 chipset
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2020-06-29 16:06:11 +02:00 |
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tiseno100
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672b0bbef7
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Deleted the Acer off the Makefile
It's not needed anymore.
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2020-06-29 16:39:30 +03:00 |
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tiseno100
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cd840c4c02
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Added the OPTi 895 in Makefile
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2020-06-29 16:38:26 +03:00 |
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tiseno100
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0b17c4ef31
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Fixed a small inconsistency
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2020-06-29 16:28:22 +03:00 |
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tiseno100
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388825377c
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Implemented the OPTi 895
Similar the OPTi 495 & 802G. It's a 486 ISA/VLB chipset used by many known boards. One being the PB450.
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2020-06-29 16:26:18 +03:00 |
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OBattler
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5c1f947122
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The VLSI VL82C480 chipset now has Port 92h, fixes the IBM PS/1 model 2133.
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2020-06-29 14:33:12 +02:00 |
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OBattler
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014552f235
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Fixes to SiS 496/497 and W83787F.
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2020-06-29 04:32:30 +02:00 |
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OBattler
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53afbfcd49
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Changed the writing of the 86f surface array to be in accordance with the pecification.
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2020-06-29 03:14:16 +02:00 |
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OBattler
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616a8501b5
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Moved floppy writeback call to fdc_poll_readwrite_finish(), in order to have the track written less often (no need to write it on every sector).
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2020-06-29 02:19:05 +02:00 |
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OBattler
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96228bc41d
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Overhauled the SiS 496/497 chipset emulation (and added the DRB locking to it) (later Zida Tomato 4DPS BIOS'es now work, and we now use the actual 1.72), fixed the W83787F and FDC37C932FR Super I/O chips, removed the no longer needed Acer M3A registers (that's now correctly handled as FDC37C932FR GPIO), and a number of bugfixes here and there.
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2020-06-29 01:10:20 +02:00 |
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OBattler
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2eceaf77e9
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Merge branch 'master' of https://github.com/86Box/86Box
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2020-06-29 00:54:02 +02:00 |
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OBattler
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ed2d8f9969
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A minor fix in floppy/fdd_86f.c .
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2020-06-29 00:53:51 +02:00 |
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RichardG867
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e3d7c07aa9
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Cosmetic changes to SMBus code
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2020-06-28 15:43:55 -03:00 |
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David Hrdlička
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af26e19b83
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workflows: disable cache, build all branches
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2020-06-28 17:55:20 +02:00 |
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David Hrdlička
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5d5b9598b2
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Jenkins test
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2020-06-28 17:18:14 +02:00 |
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David Hrdlička
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4012659fd7
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Cache the environment
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2020-06-28 16:39:09 +02:00 |
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OBattler
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645f1d42f3
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Fixed FDC sector compare finish.
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2020-06-28 13:39:29 +02:00 |
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OBattler
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926ed40741
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Sanitized some stuff in fdd_86f.c.
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2020-06-28 04:46:32 +02:00 |
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OBattler
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d5f43204c9
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Some minor changes to fdd_d86f.c.
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2020-06-27 23:27:19 +02:00 |
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David Hrdlička
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bdad12326e
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nah
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2020-06-27 17:56:02 +02:00 |
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David Hrdlička
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45b93ba4e4
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Clarify the build names
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2020-06-27 17:44:46 +02:00 |
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David Hrdlička
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1a3753377f
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Disable VNC in Workflows for now.
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2020-06-27 15:46:10 +02:00 |
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David Hrdlička
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6d059eb7e0
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Add vncserver to installed packages
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2020-06-27 15:22:17 +02:00 |
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David Hrdlička
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d66d62452f
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Add GitHub CI
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2020-06-27 15:17:53 +02:00 |
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David Hrdlička
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86183affed
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update issue templates
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2020-06-27 12:38:06 +02:00 |
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Miran Grča
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d3880e21ac
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Merge pull request #875 from richardg867/master
DRB locking fixes
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2020-06-27 03:24:15 +02:00 |
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RichardG867
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9cecbfa33a
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Remove extraneous logging lines
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2020-06-26 22:16:56 -03:00 |
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RichardG867
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7775e52c0e
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Disable SPD logging
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2020-06-26 22:15:36 -03:00 |
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RichardG867
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012f01cc9f
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Fix Apollo DRB wraparound
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2020-06-26 22:15:21 -03:00 |
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RichardG867
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3a9408eadc
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APAS3 only has 3 slots
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2020-06-26 22:14:22 -03:00 |
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RichardG867
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aea5461255
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Implement DRB locking for VIA Apollo chipsets
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2020-06-26 22:05:32 -03:00 |
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RichardG867
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0b871b56c0
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Actually fix the Apollo SS7 maximum RAM amounts, based on the DRAM bank configurations defined in the board manuals
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2020-06-26 22:02:13 -03:00 |
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RichardG867
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5a3c3a1c93
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Fix VA-503+ maximum RAM
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2020-06-26 21:32:24 -03:00 |
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RichardG867
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41c1f18c2f
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Fix PA-2012 maximum RAM
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2020-06-26 21:28:52 -03:00 |
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RichardG867
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2553dbce8f
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Unified DRB locking logic, added DRB locking to VIA VPX, and fixed SPD
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2020-06-26 21:03:46 -03:00 |
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RichardG867
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84e378695a
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Fix SPD presence detection
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2020-06-26 18:24:15 -03:00 |
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Miran Grča
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af9526b47d
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Merge pull request #873 from richardg867/master
DRB locking implementation
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2020-06-26 23:11:58 +02:00 |
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RichardG867
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93b909fe59
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Merge branch 'master' of https://github.com/86Box/86Box
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2020-06-26 18:05:57 -03:00 |
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RichardG867
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5115214d01
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DRB locking implementation
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2020-06-26 18:05:27 -03:00 |
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