Cacodemon345
9b4f98cb04
Rewritten monochrome source data handling, partially fixes text drawing under Windows 98 SE
2024-02-11 11:07:58 +06:00
maximus105
18adcb8e0e
Add files via upload
2024-02-10 11:57:40 +02:00
OBattler
4dc7342d5e
Split the NE1000 and NE2000 into the Novell and Compatible versions, with I/O base address and IRQ selections per the Windows 95 .INF file, and added the D-Link DL-220P ISA PnP NE2000 clone.
2024-02-10 04:51:07 +01:00
OBattler
951f642f42
Merge branch 'master' of https://github.com/86Box/86Box
2024-02-10 03:06:06 +01:00
OBattler
2ab99dda0b
Made LOCK instruction legality more accurate on 386, closes #4132 .
2024-02-10 03:05:56 +01:00
Miran Grča
425054228e
Merge pull request #4137 from 86Box/tc1995
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Fixed the Cirrus banking issue for good (really)
2024-02-09 18:46:14 +01:00
TC1995
a330860b2e
Fixed the Cirrus banking issue for good (really)
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A bit controversial regarding extra_banks but this should be enough to fix everything in the banks of the CL-GD54xx (up to 5480).
2024-02-09 18:28:09 +01:00
OBattler
3f8952a558
More (S)VGA horizontal blanking fixes and CPU CR0 bit 4 fixes.
2024-02-09 18:02:33 +01:00
OBattler
30e7a49558
Fix compile-breaking mistakes in cpu/386.c.
2024-02-09 12:15:28 +01:00
OBattler
5a3d74d64f
286/386 interpreter fixes - the correct opcode arrays are now used and fixed the debug registers.
2024-02-09 12:14:35 +01:00
Cacodemon345
d646efc288
Fix hardware cursor in interlaced modes
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Report 1280*1024 Dual Scan STN Color Panel for now
2024-02-09 12:44:43 +06:00
Cacodemon345
da3203a6c1
Force interlace to be off at 1280x1024
2024-02-09 00:20:59 +06:00
Cacodemon345
3e098b190e
HW cursor position fixing
2024-02-08 16:08:05 +06:00
Cacodemon345
4a087b81c6
Fix RTL BitBlt on 16+ bpp
2024-02-08 15:51:15 +06:00
Cacodemon345
a0078e6d2b
Fix inverted hardware cursor color
2024-02-08 13:22:01 +06:00
Miran Grča
c99c4ecb6e
Merge pull request #4134 from 86Box/tc1995
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Fix SVGA code warnings.
2024-02-07 23:14:25 +01:00
Cacodemon345
395941aa54
HWCursor work
2024-02-08 02:07:49 +06:00
TC1995
ca11dae903
Fix SVGA code warnings.
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See above.
2024-02-07 20:56:25 +01:00
OBattler
89cc2a3956
NEC CD-ROM: Make command DAh not also set speed.
2024-02-07 20:45:45 +01:00
Cacodemon345
5ce8b9e1a1
24-bpp image blit fixes
2024-02-08 00:34:29 +06:00
Miran Grča
c538a726c7
Merge pull request #4119 from lemondrops/feature/cpuid_and_msr
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CPUID and MSR fixes and improvements
2024-02-07 19:21:19 +01:00
Alexander Babikov
996769095b
Implement most missing P6 MSRs
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Remove the 6 extraneous performance counter MSRs which
haven't existed on P6
2024-02-07 12:31:43 +05:00
Alexander Babikov
e54b57641c
Implement missing IBM, AMD and Cyrix MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
65f40ca71d
Implement missing WinChip C6/2 and Cyrix III MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
1b9bf568f2
Implement missing Pentium MSRs
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Includes obscure behavior, like undocumented "high" MSRs
2024-02-07 12:31:41 +05:00
Alexander Babikov
8143ccdc9b
K5 reorganization
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Rename SSA/5 to Model 0 and 5k86 to Model 1/2/3 and swap their ordering
Remove the Model 0 CPUs from the Model 1 (5k86) table
2024-02-07 12:31:40 +05:00
Alexander Babikov
8520e6be85
Show actual clocks for CPUs w/ Performance Ratings
2024-02-07 12:31:40 +05:00
Alexander Babikov
2a3d13d306
Various consistency changes
2024-02-07 12:31:39 +05:00
Alexander Babikov
1e4455d98c
Add comments with MSR and CPUID flag names
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Reorganize the MSR struct
2024-02-07 12:31:38 +05:00
Alexander Babikov
b860156350
Remove an accidentally committed duplicate file
2024-02-07 12:31:38 +05:00
Alexander Babikov
1bb31f3937
Remove the AP61 hack completely
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It's no longer needed
2024-02-07 12:31:37 +05:00
Alexander Babikov
963525ff2e
Correct the CPUID SEP bit on AMD K6-2 and later
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They use the standard bit 11, not he AMD-specific bit 10
2024-02-07 12:31:37 +05:00
Alexander Babikov
aef257378e
Add PGE to AMD K5 and K6-2C/III/2+/III+
2024-02-07 12:31:36 +05:00
Alexander Babikov
37cf0b6845
Separate Pentium and Cx6x86 MSR handling
2024-02-07 12:31:35 +05:00
Alexander Babikov
a1540eee92
Remove the machine check CPUID flag from the P24T
2024-02-07 12:31:35 +05:00
Alexander Babikov
032a161c4a
Implement IDT/VIA FCR2 CPUID family/model spoofing
2024-02-07 12:31:34 +05:00
Alexander Babikov
2da7b196ac
Rename unnamed MSR vars to real names where known
2024-02-07 12:31:34 +05:00
Miran Grča
17afc7267c
Merge pull request #4131 from 86Box/tc1995
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Mach64 temporary updates:
2024-02-07 03:07:20 +01:00
TC1995
f8647f07a3
Mach64 temporary updates:
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Temporarily replace the ATI68860 8bpp renderer with a clone one while the current renderer (8bpp) is being fixed for proper colors on the Mach64.
2024-02-07 03:06:19 +01:00
Miran Grča
48fa9ba95a
Merge pull request #4130 from 86Box/tc1995
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Couple of changes in the video side.
2024-02-07 02:54:11 +01:00
TC1995
7198b78069
Couple of changes in the video side.
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1. Second attempt to fix the banking in the Cirrus (sigh, why doesn't banking get nulled automatically...)
2. Introduce a new timer to the 8514/A side so it won't slow the VGA clock down it was shared before.
2024-02-07 01:53:16 +01:00
OBattler
f3d585a1e1
Fix horizontal blanking calculation, fixes some S3 blanking excesses.
2024-02-07 00:11:02 +01:00
OBattler
d8d44efab2
Merge branch 'master' of https://github.com/86Box/86Box
2024-02-07 00:02:27 +01:00
Miran Grča
ef01e27d31
Merge pull request #4129 from 86Box/tc1995
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9001st update on Cirrus banking...
2024-02-06 23:58:10 +01:00
TC1995
30e768955c
9001st update on Cirrus banking...
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1. VRAM mask consistency...
2. Don't apply the IBM VGA mode check to linear functions, where banking isn't used at all.
2024-02-06 23:50:32 +01:00
OBattler
1b5ac0f68a
TVP3026: Correctly apply the RAMDAC multiplex mode.
2024-02-06 23:35:43 +01:00
Miran Grča
9b63f971cc
Merge pull request #4128 from 86Box/tc1995
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Update on Cirrus banking.
2024-02-06 22:58:15 +01:00
TC1995
e0aa4db151
Update on Cirrus banking.
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When I say banking should be 0 when IBM VGA modes are set, they must be, Cirrus...
Also, updated the vram mask using the gd54xx struct rather than svga's for consistency.
2024-02-06 22:44:58 +01:00
TC1995
cb4f0fe85a
Revert "HDISP updates on S3 968 cards."
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This reverts commit e648af9a71
2024-02-06 22:41:59 +01:00
TC1995
e648af9a71
HDISP updates on S3 968 cards.
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Attempt at fixing the half horizontal display bugs in the best possible way without affecting the vendor drivers (which don't enable bit 6 of gdcreg5 for 256 colors and greater but generic non-vendor specific drivers do).
2024-02-06 21:40:26 +01:00
